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[IEEE 2018 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech) - Saint Petersburg, Russia (2018.10.22-2018.10.23)] 2018 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech) - Signal Distortion Decreasing in Envelope Tracking Power Amplifiers
摘要： When amplifying signals with a high peak to average power ratio, the efficiency of linear radio frequency (RF) power amplifiers (PA) is reduced to about 30%. This flaw can be noticeably corrected by using envelope tracking technology. However, using switched mode PAs of envelope signal (ES) is accompanied by the emergence of nonlinear distortions, which can appear as undesirable components in the RF PA signal spectrum. One of the ways to reduce the negative influence of the switched mode is to use ES PA of multicell structure. The paper covers the issues of the ES PA number of cells influence on its efficiency and output signal distortion, as well as its influence on the efficiency and output signal distortion of the RF PA. It is shown that rational choice of the number of cells allows to increase the efficiency of ES PA from 94 through 98% and to reduce the level of intermodulation components in the envelope signal spectrum by 20 ... 25 dB.
关键词： envelope tracking,power amplifier,harmonic distortion,efficiency,multicell
更新于2025-09-23 15:23:52
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Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier
摘要： A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear ampli?er (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the ?ying capacitor voltage VCF and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power ampli?er (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system ef?ciency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/μs and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak ef?ciency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak ef?ciency of 91%.
关键词： long-term evolution (LTE),LTE-advanced,hysteresis control,Envelope tracking (ET),supply modulator,power ampli?er (PA),three-level switching converter (3L-SWC),slew-rate enhancement (SRE),hybrid
更新于2025-09-19 17:13:59
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Partial Least Squares Identification of Multi Look-Up Table Digital Predistorters for Concurrent Dual-Band Envelope Tracking Power Amplifiers
摘要： This paper presents a technique to estimate the coefficients of a multiple-look-up table (LUT) digital predistortion (DPD) architecture based on the partial least-squares (PLS) regression method. The proposed 3-D distributed memory LUT architecture is suitable for efficient FPGA implementation and compensates for the distortion arising in concurrent dual-band envelope tracking power amplifiers. On the one hand, a new variant of the orthogonal matching pursuit algorithm is proposed to properly select only the best LUTs of the DPD function in the forward path, and thus reduce the number of required coefficients. On the other hand, the PLS regression method is proposed to address both the regularization problem of the coefficient estimation and, at the same time, reducing the number of coefficients to be estimated in the DPD feedback identification path. Moreover, by exploiting the orthogonality of the PLS transformed matrix, the computational complexity of the parameters’ identification can be significantly simplified. Experimental results will prove how it is possible to reduce the DPD complexity (i.e., the number of coefficients) in both the forward and feedback paths while meeting the targeted linearity levels.
关键词： principal component analysis (PCA),look-up tables (LUTs),power amplifier (PA),envelope tracking (ET),partial least squares (PLS),Digital predistortion (DPD)
更新于2025-09-09 09:28:46