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Border trap evaluation for SiO <sub/>2</sub> /GeO <sub/>2</sub> /Ge gate stacks using deep-level transient spectroscopy
摘要： A border trap (BT) evaluation method was established for SiO2/GeO2/Ge gate stacks by using deep-level transient spectroscopy with a lock-in integrator. Ge metal-oxide-semiconductor capacitors (MOSCAPs) with SiO2/GeO2/Ge gate stacks were fabricated by using different methods. The interface trap (IT) and BT signals were successfully separated based on their different dependences on the intensity of injection pulses. By using p-type MOSCAPs, BTs at the position of 0.4 nm from the GeO2/Ge interface were measured. The energy of these BTs was centralized at the position near to the valence band edge of Ge, and their density (Nbt) was in the range of 1017–1018 cm?3. By using n-type MOSCAPs, BTs at the position range of 2.8–3.4 nm from the GeO2/Ge interface were measured, of which Nbt varied little in the depth direction. The energy of these BTs was distributed in a relatively wide range near to the conduction band edge of Ge, and their Nbt was approximately one order of magnitude higher than those measured by p-MOSCAPs. This high Nbt value might originate from the states of the valence alternation pair with energy close to 1 eV above the conduction band edge of Ge. We also found that Al post metallization annealing can passivate both ITs and BTs near to the valence band edge of Ge but not those near to the conduction band edge.
关键词： deep-level transient spectroscopy,valence band edge,conduction band edge,interface trap,border trap,Ge metal-oxide-semiconductor capacitors
更新于2025-09-09 09:28:46
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Experimental Characterization of the Influence of Transverse Prestrain on the Piezoresistive Coefficients of Heavily Doped n-Type Silicon
摘要： Strain has been integrated into many silicon devices, as it has an essential impact on carrier mobility and crystal symmetry. Those parameters respond differently under both biaxial and uniaxial, so their effect needs to be quantified to successfully employ the strain engineering in different silicon applications. As an extended step toward utilizing strain in enhancing the sensitivity and the temperature independency of a 3-D stress sensor, the effect of uniaxial transverse strain onto the piezoresistive (PR) coefficients of heavily doped n-type silicon will be experimentally characterized. A new design was developed to apply the transverse tensile and compressive uniaxial stresses onto the silicon substrate using a highly compressive nitride layer. This stressing technique was integrated with six PR elements rosette to fully calibrate the PR coefficients, where unstrained, tensile, and compressive strained PRs are fabricated within the same chip to accurately quantify the strain impact. Four-point bending, stress-free temperature, and hydrostatic test were used to typically measure the PR coefficients. Strain values of 0.065% and 0.083% ε were achieved locally using both the tensile and compressive stressors, respectively. Under this level of strain, the typical result shows opposite impact for both the tensile and compressive transverse strains on the longitudinal and transverse PR coefficients. Moreover, an increase up to 80% can be achieved for the pressure coefficient of heavily doped n-type silicon due to the compressive transverse strain.
关键词： metal–oxide–semiconductor (MOS) local transistors,3-D piezoresistive (PR) sensor,n-type silicon,strain,strain engineering,piezoresistivity
更新于2025-09-09 09:28:46
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[Lecture Notes in Computer Science] Neural Information Processing Volume 11307 (25th International Conference, ICONIP 2018, Siem Reap, Cambodia, December 13–16, 2018, Proceedings, Part VII) || Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition
摘要： Arti?cial intelligences are essential concepts in smart societies, and neural networks are typical schemes that imitate human brains. However, the neural networks are conventionally realized using complicated software and high-performance hardware, and the machine size and power consumption are huge. On the other hand, neuromorphic systems are composed solely of optimized hardware, and the machine size and power consumption can be reduced. Therefore, we are investigating neuromorphic systems especially with amorphous metal-oxide semiconductor (AOS) thin-?lm devices. In this study, we have developed a Hop?eld neural network with double-layer AOS thin-?lm devices as crosspoint-type synapse elements. Here, we propose modi?ed Hebbian learning done locally without extra control circuits, where the conductance deterioration of the crosspoint-type synapse elements can be employed as synaptic plasticity. In order to validate the fundamental operation of the neuromorphic system, ?rst, double-layer AOS thin-?lm devices as crosspoint-type synapse elements are actually fabricated, and it is found that the electric current continuously decreases along the bias time. Next, a Hop?eld neural network is really assembled using a ?eld-programmable gate array (FPGA) chip and the double-layer AOS thin-?lm devices, and it is con?rmed that a necessary function of the letter recognition is obtained after learning process. Once the fundamental operations are con?rmed, more advanced functions will be obtained by scaling up the devices and circuits. Therefore, it is expected the neuromorphic systems can be three-dimensional (3D) large-scale integration (LSI) chip, the machine size can be compact, power consumption can be low, and various functions of human brains will be obtained. What has been developed in this study will be the sole solution to realize them.
关键词： Neural network,Hop?eld neural network,Letter recognition,Arti?cial intelligence,Crosspoint-type synapse elements,Double-layer amorphous metal-oxide semiconductor (AOS) thin-?lm device,Modi?ed hebbian learning
更新于2025-09-09 09:28:46
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P-1.10: Solution-processed metal oxide semiconductors fabricated with oxygen radical assisting perchlorate aqueous precursors through a new low-temperature reaction route
摘要： In this report, an innovative and simple chemical route for fabricating MO semiconducting low temperature without any fuel additives or special annealing methods is demonstrated. Different from combustion method, the precursor that we compound contains only two kinds of oxidizers. The precursor, which consisted of perchlorate, nitrate, and DI water, is easily converted into In2O3 at an annealing temperature of 250 °C due to oxygen radical assisting decomposition and large amount of heat generation. It is found that perchlorate salt can decompose and form oxide film with high quality at lower temperature when assisted by nitrate salt. The optimized In2O3-TFT fabricated at 250°C via this precursor exhibits a saturate mobility of 14.5 cm2V-1s-1. Furthermore, this approach has been expanded to fabrication films at 350°C and attained improved performance.
关键词： metal oxide semiconductor,perchlorate salt,solution-process,oxygen radical,Thin-film transistor
更新于2025-09-09 09:28:46
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Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high- <i>k</i> /n-InGaAs metal-oxide-semiconductor stacks
摘要： The correlation between capacitance-voltage hysteresis and accumulation capacitance frequency dispersion of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks is experimentally assessed. Samples fabricated employing forming gas annealing (FGA) or substrate air exposure to obtain different densities of defects were thoroughly characterized and the results were compared with previous literature on the topic. Results indicate a lack of correlation between capacitance-voltage hysteresis and accumulation capacitance dispersion with frequency, suggesting that defects with remarkably different kinetics are involved in each phenomenon. This is assessed through the dependence of the capacitance-voltage hysteresis with DC bias and stress time, observing that permanent interface defect depassivation under bias has no effect on the hysteresis width after stress. Overall, capacitance-voltage hysteresis probes slow trapping mechanisms throughout the oxide and the bandgap, which are consistent with the negative charge trapping characteristic of the current-time curves for FGA samples at constant voltage stress. Instead, accumulation capacitance frequency dispersion probes defects with short trapping/detrapping characteristic times that can be linked to the stress induced leakage current of air exposed samples under constant DC stress. Experimental results indicate that each effect must be assessed separately due to the large difference in the kinetics of the probed defects.
关键词： metal-oxide-semiconductor stacks,forming gas annealing,defects,metal gate/high-k/n-InGaAs,trapping mechanisms,capacitance-voltage hysteresis,accumulation capacitance frequency dispersion
更新于2025-09-04 15:30:14