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- 实验方案
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Investigation of the performance of strain-engineered silicon nanowire field effect transistors (?-Si-NWFET) on IOS substrates
摘要： In the current work, a design space for developing the performance enhanced strain-engineered Si nanowire field-effect-transistors has been provided. The fraction of insertion of the nanowire channel into the Insulator-on-Silicon substrate with judicious selection of high-k gate insulators is used as the key design parameter. The combined effect of fractional insertion and gate insulators results in inducing stress into the nanowire channel and, depending on their selection, it changes from tensile to compressive. Such induced-stress alters the existing inherent phononic-stress, leading to the modification of the carrier transport in the device channel. The carrier transport behavior in such partially embedded nanowire FETs has been modeled by incorporating the relevant stress-related effects into the indigenously developed self-consistent quantum-electrostatic framework. These equations are solved by employing the non-equilibrium Green’s function formalism. The study shows the phonon scattering under tensile strain to occur at the expense of electron energy; however, the electrons can also gain energy during such scattering in compressive stress. Thus, the device current has been observed to increase with tensile stress and it achieves relatively smaller values when the inherent tensile phononic stress is balanced by the induced compressive stress. However, the current is finally observed to increase once the compressive stress overcomes the inherent tensile phononic stress. In general, the present devices exhibit promising Ion/Ioff ratio for all of the fractional insertions and gate dielectrics with a maximum Ioff of <10 nA/μm, threshold voltage of sub-0.3 V, gm of ～104 μS/μm, sub-threshold swing of ～100 mV/dec, and drain-induced-barrier-lowering of ～100 mV/V.
关键词： IOS substrates,high-k gate insulators,strain-engineered,silicon nanowire,non-equilibrium Green’s function,quantum-electrostatic framework,field-effect transistors
更新于2025-09-10 09:29:36
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX, USA (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Toward more realistic NEGF simulations of vertically stacked multiple SiNW FETs
摘要： We present quantum transport simulation results of vertically stacked multiple silicon nanowire (SiNW) FETs based on the non-equilibrium Green’s function (NEGF) method. In order to consider more realistic device conditions such as complex geometry of the multi-channel FETs and various carrier scattering processes, we improved physical models and numerical techniques for the NEGF simulations.
关键词： non-equilibrium Green’s function (NEGF),quantum transport,multiple nanowire FET
更新于2025-09-09 09:28:46
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX, USA (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Carrier Transport in a Two-Dimensional Topological Insulator Nanoribbon in the Presence of Vacancy Defects.
摘要： We model transport through two-dimensional topological insulator (TI) nanoribbons. To model the quantum transport, we employ the non-equilibrium Green’s function approach. With the presented approach, we study the effect of lattice imperfections on the carrier transport. We observe that the topologically protected edge states of TIs are robust against a high percentage (2%) of vacancy defects. We also investigate tunneling of the edge states in two decoupled TI nanoribbons.
关键词： nanoribbon,vacancy defects,non-equilibrium Green’s function,carrier transport,two-dimensional topological insulator
更新于2025-09-04 15:30:14
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX, USA (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications
摘要： New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and Ion/Ioff > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.
关键词： DFT,tunnel FETs,Non-equilibrium Green’s Function,TMDCs,black phosphorus,Two-dimensional Materials Heterojunctions
更新于2025-09-04 15:30:14