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An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
摘要： An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.
关键词： on-chip monitoring circuit,sub-sampling,chip-to-chip interface,analog-to-digital converter,phase-locked loop-based frequency synthesizer
更新于2025-09-23 15:22:29
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[IEEE 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII (TRANSDUCERS & EUROSENSORS XXXIII) - Berlin, Germany (2019.6.23-2019.6.27)] 2019 20th International Conference on Solid-State Sensors, Actuators and Microsystems & Eurosensors XXXIII (TRANSDUCERS & EUROSENSORS XXXIII) - Infrared Photodetector with Copper Resonator in Silicon Nanohole Array
摘要： A highly linear broadband photonic-assisted analog-to-digital converter (ADC) based on high-frequency optical sampling utilizing a dual output Mach–Zehnder modulator operating with signal frequencies up to 50 GHz is presented. The pulses employed in the optical sampling were generated by a cavity-less pulse source operated at 10 GHz in preference to conventional mode-locked lasers. The optical sampling front-end greatly extends the operational frequency range of the Nyquist limited electronic digitization back-end. The performance of the sampling system is characterized with 7.1 effective number of bits (ENOBs) at 40 with 5 GHz fully accessible bandwidth, and greater than 99 dB·Hz2/3 spurious free dynamic range for the 30–40 GHz frequency range. Furthermore, more than 8 ENOB was achieved by reducing the effective bandwidth to 1 GHz with a digital ?lter, demonstrating the additional advantage of using a higher sampling rate compared to previous demonstrations. A new ?gure of merit of photonic-assisted sub-sampled ADCs is also presented accompanied with a comparison to previous implementations.
关键词： microwave photonics,optical data processing,sampling,Analog-digital conversion,detection,sub-sampling,optical ?ber communications
更新于2025-09-23 15:19:57
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Technological Features of Graphene-based RF NEMS Capacitive Switches on a Semi-insulating Substrate
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - A Compact Octa-band Antenna for Handsets Application
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - Tehran, Iran (2018.12.18-2018.12.20)] 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - MMWaTT 2018 Organizing Committee
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： frequency synthesizer,sub-sampling,CMOS,voltage-domain,analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 Photonics North (PN) - Quebec City, QC, Canada (2019.5.21-2019.5.23)] 2019 Photonics North (PN) - Differences between foetal and adult meniscus and cartilage revealed by Polarization Second Harmonic Generation Microscopy
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),voltage-domain,sub-sampling,frequency synthesizer,low-power,CMOS
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - Waltham, MA, USA (2019.10.15-2019.10.18)] 2019 IEEE International Symposium on Phased Array System & Technology (PAST) - A Low Profile Tightly Coupled Antenna Array with 80?° Scanning for Multifunctional Applications
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59