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Design Optimization of Photovoltaic Cell Stacking in a Triple-Well CMOS Process
摘要： Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25-μm standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm2 under an incident illumination with an intensity of 96 μW/mm2, achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.
关键词： on-chip solar cell,photovoltaic (PV) cell stacking,Energy harvesting,voltage boosting
更新于2025-09-23 15:21:01
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An Integrated Semi-Double Stage based Multilevel Inverter with Voltage Boosting Scheme for Photovoltaic Systems
摘要： This paper proposes a single-phase, seven-level, transformerless inverter, employing a semi-double stage based conversion technique, which is particularly suitable for PV applications. The proposed configuration achieves voltage boosting using a non-isolated interleaved buck-boost converter, which is fused with the inverter configuration through two switched capacitors (SC). The interleaved front-end boost stage is capable of achieving a voltage gain of three while resulting in reduced peak current stress on the switching devices. In this topology, a part of the load power is transferred directly from the PV source, while the other part is transferred through the SCs. The proposed topology and the associated PWM technique are capable of reducing the leakage current by isolating the terminals of the PV source during the freewheeling state. This paper also presents a thorough analysis of the stray capacitor voltage and the common-mode voltage (CMV). These analyses reveal that the high-switching frequency transitions are eliminated in both of these waveforms. Furthermore, the proposed topology results in the reduction of the low-frequency transitions in the stray capacitor voltage and the CMV, which results in further reduction of the leakage current. The simulation and experimental results are in agreement with the mathematical analysis of the proposed inverter.
关键词： Leakage current minimization,Pulse width modulation inverters,Multilevel-inverter,Voltage boosting,Semi-double stage system,Photovoltaic systems
更新于2025-09-11 14:15:04