研究目的
Investigating the failure configuration type of BRAM in read operation and isolating the fault using pattern analysis.
研究成果
The pattern analysis in Vivado is an effective and efficient debugging methodology for isolating BRAM failures. The PFA findings proved the fault isolation hypotheses, confirming the effectiveness of the approach.
研究不足
The complexity of BRAM architecture and configuration increases the difficulty of fault isolation. The failure analysis is largely dependent on pattern analysis to screen out the failure configuration types.
1：Experimental Design and Method Selection:
The methodology involved using ATE to screen out the failure configuration types of BRAM in read operation. The failure pattern was created in Vivado with ILA inserted to monitor the failure BRAM data and compare it against good BRAM data.
2：Sample Selection and Data Sources:
The FPGA device failing BRAM 18K x 2 in read first operation at high temperature was selected based on ATE data log.
3：List of Experimental Equipment and Materials:
ATE, Vivado tools, ILA, and FPGA devices were used.
4：Experimental Procedures and Operational Workflow:
The original BRAM full pattern source code was modified to involve only two BRAMs in the test. ILA was used to monitor various signals and compare between good and failing BRAMs.
5：Data Analysis Methods:
The data was analyzed by comparing the output signals monitored by ILA in Vivado, focusing on the failure pattern when reading memory from high address to low address.
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