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A Multi-Phase Switched-Capacitor Converter for Fully Integrated AMLED Micro Display System

DOI:10.1109/tpel.2019.2951799 期刊:IEEE Transactions on Power Electronics 出版年份:2019 更新时间:2025-09-16 10:30:52
摘要: A fully-integrated switched-capacitor (SC) DC-DC converter is designed for powering up an active-matrix light-emitting diode (AMLED) micro-display system. Stacking-transistor technique with three voltage conversion ratios is utilized to handle the lithium-ion battery range of 2.6 V to 4.2 V and to reduce the switching loss. A 101-phase interleaving scheme is adopted such that (1) output voltage ripple ΔVO is significantly reduced; (2) no external output capacitor is needed; and (3) SC power-cells are physically cascaded to encircle the LED array and drivers to reduce conduction loss. Two test chips were designed in 0.18 μm 1P6M CMOS technology. The first chip is a test chip consisted of the SC converter only. The output voltage is 4.2V and the measured maximum ΔVO is 52 mV. The measured power density is 74.4 mW/mm2, peak efficiency is 81%, and maximum output power is 258 mW. The second chip is a system chip integrating the SC converter with the AMLED array and drivers using flip-chip packaging. The converter delivers a maximum power of 216 mW with a 78% peak efficiency in the SC mode and a 91% peak efficiency in the linear regulator mode.
作者: Junmin Jiang,Xun Liu,Wing-Hung Ki,Philip K. T. Mok,Yan Lu
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To design a fully-integrated switched-capacitor DC-DC converter for powering an active-matrix light-emitting diode (AMLED) micro-display system, capable of handling a wide input voltage range (2.6 V to 4.2 V) with high efficiency and low output voltage ripple.

The proposed fully-integrated switched-capacitor DC-DC converter successfully powers an AMLED micro-display system with high efficiency (81% peak) and low output voltage ripple (1.23% of the output voltage). The use of a 101-phase interleaving scheme and stacking-transistor technique effectively handles the wide input voltage range of a Li-ion battery and reduces switching loss. The design demonstrates a significant improvement in power density and efficiency compared to state-of-the-art solutions, making it suitable for portable and low-power applications.

The design is limited by the CMOS process technology, which affects the maximum achievable efficiency and power density. The use of thin-oxide transistors, while reducing switching loss, requires careful design to handle high voltage stresses. The number of interleaving phases is constrained by the layout and clock distribution challenges.

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