研究目的
To trace the important contributions made to modern Boolean satisfiability solvers by the electronic design automation community to address synthesis and verification problems, and discuss its applications in model checking.
研究成果
The paper concludes that SAT solving and hardware model checking have a history of mutually beneficial development. Techniques developed by the EDA community have revolutionized satisfiability checking, and the resulting performance boost of SAT solvers has significantly advanced model checking, enabling its application to industrial-size designs. The paper anticipates continued progress in both fields, driven by initiatives like the SAT competition and the hardware model checking competition, and highlights parallelism as a promising frontier for future research.
研究不足
The paper focuses on finite-state model checking exclusively and does not cover software verification techniques. It also highlights the state explosion problem in model checking as a significant limitation.