研究目的
To design a Coarse-Grained Reconfigurable Architecture (CGRA) processor that balances energy consumption and reliability requirements through user programmable redundancy.
研究成果
The EReLAv1 prototype demonstrates that programmable redundancy can effectively balance robustness and power efficiency. Level1 redundancy extends MTTF by 4.4 times with minimal power increase, while level2 avoids over-design in conventional DMR methods, achieving better energy efficiency without sacrificing data coverage.
研究不足
The prototype chip has unprotected DFFs not covered by device hardening or ECC, leading to potential undetected errors. The design lacks power gating, affecting power consumption differences between redundancy levels.
1：Experimental Design and Method Selection:
The study involves designing a CGRA processor named EReLA with software and hardware approaches for fault tolerance.
2：Sample Selection and Data Sources:
A prototype processor, EReLAv1, was implemented and manufactured with a CMOS technology.
3：List of Experimental Equipment and Materials:
The prototype chip was tested using an alpha particle source, 3 Mbq 241Am, for irradiation tests.
4：Experimental Procedures and Operational Workflow:
Stress tests based on alpha particle irradiation were conducted to verify the tradeoff between robustness and power efficiency.
5：Data Analysis Methods:
The results were analyzed in terms of mean-time-to-failure (MTTF) and power consumption.
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