研究目的
Developing a GaN vertical trench MOSFET with normally-off operation for power electronics applications.
研究成果
A GaN vertical trench MOSFET with normally-off operation was developed, featuring a threshold voltage of 4.8 V, a blocking voltage of 600 V at gate bias of 0 V, and on-resistance of 1.7 Ω at gate bias of 10 V. The device characteristics were enabled by an AlN/SiN gate dielectric process and a source regrowth process to allow proper body contact.
研究不足
The large cell pitch size and/or the channel resistance are limiting factors of the total on-resistance. Improvement of total on-resistance can be achieved by reducing the cell pitch size, improving the dielectric/semiconductor interface quality, and optimizing the drift layer growth condition for better electron mobility.
1：Experimental Design and Method Selection:
The process started with MOCVD growth of n?-GaN drift layer and p-GaN base layer on a bulk GaN substrate. Selective area regrowth of n+-GaN was performed, using patterned SiO2 as the regrowth mask. Gate trenches were formed by Cl-based ICP etch, followed by a TMAH wet etching treatment. An AlN/SiN dielectric stack was grown by MOCVD as the gate dielectric.
2：Sample Selection and Data Sources:
The drift layer is about 8 μm thick with a Si doping concentration of 1～2×1016 cm?
3：The base layer is about 800 nm thick with a Mg concentration of ～2×1018 cm?List of Experimental Equipment and Materials:
MOCVD for GaN growth, ICP etcher for gate trench formation, TMAH for wet etching, AlN/SiN dielectric stack for gate dielectric.
4：Experimental Procedures and Operational Workflow:
The process included regrowth of n+-GaN, gate trench formation, dielectric deposition, contact via opening, body contact formation, and metallization for source, gate, and drain electrodes.
5：Data Analysis Methods:
On-wafer DC IV characterization was performed using an Agilent B1505A power device analyzer.
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