摘要： Thin film transistor (TFTs) based integrated circuits on flexible substrates promise interesting approaches to human interface systems. TFTs have been fabricated on textured surfaces such as textiles, paper, artificially corrugated substrates and fibers. This can result in the metal-insulator-semiconductor (MIS) stack being significantly distorted from a planar geometry to having high curvature. Although the direct deposition on textured surfaces does not result in mechanical stress (as opposed to that seen during bending, buckling, wrinkling), the geometry of high curvature can influence the characteristics of the TFT. Here we present a closed form analytical model describing the impact of high curvature on the electrical performance of the TFT. Models are obtained from the solution to the Poisson-Boltzmann equation in polar co-ordinates and are limited to cylindrical surface (zero Gaussian curvature) with the ratio of radius of curvature of the semiconductor-insulator interface, rsi, to insulator thickness, ti, ranging from rsi/ti = 2 to rsi/ti = 50. Models are verified using Technology Computer-Aided Design (TCAD) simulations performed using amorphous galium indium zinc oxide (a-GIZO). Studies show that when the semiconductor-insulator interface is curved convex (normal vector into the gate) the interfacial free carrier concentration increases by 50% (for rsi/ti = 2) to 8.5% (for rsi/ti = 15) as compared to planar TFTs. On the other hand, when the curvature is concave, the free carrier concentration decreases by those percentages as compared to planar TFTs. Thus curvature can modulate TFT transconductance. Models show that the impact of curvature becomes negligible (< 4% variation) for rsi/ti > 25. Techniques to generalize the results to periodic cylindrical surfaces and other semiconducting materials are discussed along with experimental verification. This work forms an analytical basis to understand the behavior of TFTs fabricated on textured substrates.