摘要： Palladium has been widely employed as a hole contact to WSe2 and has enabled, at times, the highest WSe2 transistor performance. However, there are orders of magnitude variation across the literature in Pd–WSe2 contact resistance and ION/IOFF ratios with no true understanding of how to consistently achieve high–performance contacts. In this work, WSe2 transistors with impressive ION/IOFF ratios of 106 and Pd–WSe2 Schottky diodes with near–zero variability are demonstrated utilizing Ohmic–like Pd contacts through deliberate control of the interface chemistry. The increased concentration of a PdSex intermetallic is correlated with an Ohmic band alignment and concomitant defect passivation, which further reduces the contact resistance, variability, and barrier height inhomogeneity. The lowest contact resistance occurs when a 60 minute post metallization anneal at 400 °C in forming gas (FG) is performed. X-ray photoelectron spectroscopy indicates this FG anneal produces 3× the concentration of PdSex and an Ohmic band alignment, in contrast to that detected after annealing in ultra–high vacuum, during which a 0.2 eV hole Schottky barrier forms. Raman spectroscopy and scanning transmission electron microscopy highlight the necessity of the fabrication step to achieve high–performance contacts as no PdSex forms and WSe2 is unperturbed by room temperature Pd deposition. However, at least one WSe2 layer is consumed by the necessary interface reactions that form PdSex requiring strategic exploitation of a sacrificial WSe2 layer during device fabrication. The interface chemistry and structural properties are correlated with Pd–WSe2 diode and transistor performance and the recommended processing steps are provided to enable reliable high–performance contact formation.