研究目的
Investigating the effects of parasitic capacitance on both the static and dynamic electrical characteristics of back-gated two-dimensional semiconductor negative-capacitance field-effect transistors (NC-FETs).
研究成果
The study systematically investigates the effects of parasitic capacitance on both the static and dynamic electrical characteristics of back-gated 2D NC-FETs using an analytical drain-current model. It finds that parasitic capacitance contributes to the reduction in subthreshold swing but leads to a larger dynamic hysteresis, necessitating a balance between SS and switching speed in real device applications.
研究不足
The study focuses on back-gated 2D NC-FETs with specific materials and configurations, and the findings may not be directly applicable to other types of NC-FETs or materials. The dynamic hysteresis caused by the damping term of the FE layer is not eliminated in actual DC measurement processes.
1：Experimental Design and Method Selection:
The study proposes a unified analytical drain-current model for back-gated two-dimensional (2D) NC-FETs for both static and dynamic simulations, calibrated to experimental data.
2：Sample Selection and Data Sources:
Two back-gated MoS2 NC-FETs with different thicknesses of MoS2 were fabricated.
3：List of Experimental Equipment and Materials:
The gate stack includes heavily doped Si as the gate electrode, 20 nm Hf
4：5Zr5O2 (HZO) as the FE capacitor, and 2 nm Al2O3 as the capping layer and capacitance-matching layer. Experimental Procedures and Operational Workflow:
The effects of parasitic capacitance on the static and dynamic electrical characteristics were investigated systematically based on the model.
5：Data Analysis Methods:
The study includes the extraction of Landau coefficients from the experimental polarization–electric field (P–E) curve and comparison of simulated results with experimental measurements.
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