研究目的
To develop a low-temperature process for the homoepitaxial growth of antimony superlattices in silicon for device passivation, achieving high dopant densities and sharp dopant profiles.
研究成果
The authors have developed an 'all low-temperature' growth process for antimony delta-doped silicon compatible with fully-fabricated detectors. The process achieves high dopant concentrations with extremely narrow distributions, suggesting the upper limit for dopant incorporation and activation has not yet been met. Future work includes integrating these n-type superlattice structures with live photodetectors for evaluation and optimization.
研究不足
The high temperature annealing steps employed by various groups are not compatible with 'live,' foundry finished devices due to concerns related to Si-metal interdiffusion, delamination at wafer-to-wafer bond interfaces, and potential depassivation of the front-surface oxide.
1:Experimental Design and Method Selection:
Low-temperature molecular beam epitaxy (MBE) was used to embed atomically thin, highly concentrated layers of dopant atoms within nanometers of the silicon surface. The process was optimized for sharp dopant profiles and high dopant densities.
2:Sample Selection and Data Sources:
High purity silicon substrates (n-type, >5000 Ω cm) were used. The wafers were treated with an RCA-type clean and UV ozone exposure before MBE growth.
3:List of Experimental Equipment and Materials:
Veeco Gen 200 MBE system, valved cracker cell for antimony evaporation, electron beam evaporation for silicon deposition, and re?ection high energy electron diffraction (RHEED) for in situ monitoring.
4:Experimental Procedures and Operational Workflow:
The substrate was slowly heated to 425 °C with intermediate low-temperature soak steps. An undoped silicon buffer layer was deposited, followed by antimony delta layer growth at varying substrate temperatures. The structure was capped with silicon.
5:Data Analysis Methods:
Secondary ion mass spectrometry (SIMS) for depth profiling, Hall Effect and contactless sheet resistance measurements for electrical characterization.
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