研究目的
Investigating the impact of parasitic capacitors on the switching performance of 10 kV SiC MOSFETs in a converter setup.
研究成果
The study concludes that parasitic capacitors significantly impact the switching performance of 10 kV SiC MOSFETs, slowing down both turn-on and turn-off transients and increasing switching energy losses. The impact is more pronounced at light load conditions, with the parasitic capacitor due to the heat sink design causing up to 44.5% increase in switching energy loss at low load current.
研究不足
The study is limited to room temperature conditions and does not explore the effects of temperature variations on the parasitic capacitors' impact. Additionally, the focus is on discrete 10 kV SiC MOSFETs, and the findings may not directly apply to module-based configurations.
1：Experimental Design and Method Selection:
A half bridge phase leg test setup is built to investigate the impact of parasitic capacitors on the switching performance at 6.25 kV. The methodology includes detailed procedures of the experimental methods to analyze the parasitic capacitors caused by the anti-parallel JBS diode, heat sink, and load inductor.
2：25 kV. The methodology includes detailed procedures of the experimental methods to analyze the parasitic capacitors caused by the anti-parallel JBS diode, heat sink, and load inductor.
Sample Selection and Data Sources:
2. Sample Selection and Data Sources: The test setup consists of two 10 kV SiC MOSFETs from Wolfspeed/Cree, with a focus on the parasitic capacitors introduced by the load inductor and the heat sink design.
3：List of Experimental Equipment and Materials:
The setup includes a high voltage load inductor, gate drive board with desat protection, dc-link capacitor, and busbar. Measurement equipment includes a 75 MHz high voltage passive probe from Tektronix and a current probe for accurate current measurement.
4：Experimental Procedures and Operational Workflow:
DPT is conducted at room temperature with careful grounding scheme design. The impact of parasitic EPC in the load inductor and the heat sink on the switching performance is analyzed through varying the parasitic EPC and comparing two different thermal designs.
5：Data Analysis Methods:
The analysis focuses on the switching transients and losses, with emphasis on the turn-on and turn-off energy loss and dv/dt, using normalized data to clearly indicate the impact of parasitic capacitors.
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