1：Experimental Design and Method Selection:

The study involved designing and fabricating 4H-SiC-based ESD protection circuits, including conventional GGNMOS, FBNMOS, and the proposed gate-body floating NMOS (GBFNMOS). Electrical characteristics were analyzed using transmission-line pulse (TLP) testing with a rising time of 10 ns and pulse width of 100 ns. Thermal reliability was measured at temperatures from 300 to 500 K.

2：Sample Selection and Data Sources:

Devices were fabricated on a N+ substrate on a 4H-SiC wafer with specific doping concentrations and depths as summarized in Table I. All devices had the same geometry and gate oxide thickness of 500 ?.

3：List of Experimental Equipment and Materials:

Equipment included TLP test setup, RTP process equipment for silicide formation, and DC sputtering for Ni metal deposition. Materials included 4H-SiC wafers, nitrogen and aluminum for doping, and Ni for ohmic contacts.

4：Experimental Procedures and Operational Workflow:

Fabrication involved implanting nitrogen for N-type and aluminum for P-type regions at 650°C, silicide processing with Ni at 1050°C for 30 s, and forming ohmic contacts. TLP measurements were conducted to obtain I-V characteristics, and thermal tests were performed at elevated temperatures.

5：Data Analysis Methods:

I-V curves from TLP tests were compared to evaluate trigger voltage, holding voltage, on-resistance, and secondary breakdown current (It2). Thermal data were analyzed for heat loss rates.