研究目的
To introduce a new circuit-level idea for driving optrodes in an optical stimulation system, aiming to make the stimulation circuitry energy efficient based on adiabatic circuits, and to develop and test a prototype stimulation circuit and a micro-fabricated optrode array for multi-channel optical stimulation in a semi-implantable optogenetic system.
研究成果
The proposed adiabatic stimulation circuit achieves approximately 66% energy saving compared to a basic circuit, which is crucial for implantable devices due to reduced power consumption. The microfabricated optrode array with blue OLEDs is successfully developed and tested, demonstrating feasibility for optogenetic applications. Future work could focus on further optimization, integration with wireless systems, and in vivo validation to enhance practicality and performance.
研究不足
The circuit design relies on specific component values (e.g., C1=0.5 μF, C2=1.5 μF, RT1=4 kΩ, RT2=5.8 kΩ) and assumptions (e.g., VD,ON=0.7V, VM=2.3V), which may limit generalizability. The energy saving of ~66% is theoretical and based on simulations and calculations; practical implementations might face issues like parasitic effects, temperature variations, or scalability to larger arrays. The optrode array is microfabricated but tested only electrically; in vivo or biological testing is not reported, indicating potential application constraints in real implantable systems.
1：Experimental Design and Method Selection:
The methodology involves designing an adiabatic stimulation circuit based on energy recycling concepts from digital VLSI, using a charge phase and two stimulation cycles (SC-I and SC-II) to drive optrodes efficiently.
2：Sample Selection and Data Sources:
A microfabricated optrode array with OLEDs on a flexible PET substrate is used, designed with specific mask patterns and tested electrically.
3：List of Experimental Equipment and Materials:
Includes storage capacitor C1 (
4：5 μF), energy saver capacitor C2 (5 μF), NMOS transistors for switches, a timing sequence generator, analog comparator, and off-the-shelf discrete components for prototyping. Experimental Procedures and Operational Workflow:
The circuit operates in phases: Charge Phase (precharge C1 to VM), SC-I (connect C1 to optrode and C2 for current flow), and SC-II (recycle energy from C2). Timing is controlled by a TSG block. Simulations are done in a
5：2). Timing is controlled by a TSG block. Simulations are done in a 18-μm CMOS technology, and physical layout and post-layout simulations are performed. Functional experiments use an oscilloscope to measure voltages. Data Analysis Methods:
0.18-μm CMOS technology, and physical layout and post-layout simulations are performed. Functional experiments use an oscilloscope to measure voltages. 5. Data Analysis Methods: Energy saving is calculated using derived equations (5)-(8) based on voltage decays and resistances, with comparisons to a basic circuit from prior work.
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