研究目的
To present a large-scale timing synchronization scheme for scalable phased arrays, utilizing a hybrid DLL co-designed with a PLL to reduce in-band rms jitter and improve performance over prior works.
研究成果
The hybrid DLL/PLL scheme achieves an order-of-magnitude improvement in in-band rms jitter (323fs) compared to prior works, demonstrating effective noise reduction through co-design and novel architectural techniques. It is suitable for large-scale phased array clock distribution with low power consumption and small area.
研究不足
The DLL's frequency range is limited by maximum DCDL delay and overflow actuation timing accuracy. Lock time is not optimized for fast applications, and performance degrades at frequencies away from the optimized 50MHz due to increased noise or reduced PLL noise rejection.
1：Experimental Design and Method Selection:
The hybrid DLL architecture uses a digitally controlled delay line (DCDL) for coarse tuning and a variable delay line (VDL) for fine tuning, with an analog DLL control loop and overflow detection for stability. It is co-designed with a PLL for noise optimization.
2：Sample Selection and Data Sources:
The DLL and PLL were fabricated in a 65nm bulk CMOS process and tested with input reference frequencies from 27MHz to 270MHz.
3：List of Experimental Equipment and Materials:
Keysight PXA N9030B signal analyzer for phase noise measurements, fabricated CMOS chips.
4：Experimental Procedures and Operational Workflow:
The DLL was characterized by measuring phase noise, rms jitter, control voltage, and delay between reference and output signals under different loads and frequencies. Cascaded DLL tests were performed to estimate noise contributions.
5：Data Analysis Methods:
Phase noise spectral density was measured, rms jitter was calculated from phase noise profiles, and linear fits were used for cascade noise analysis.
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