研究目的
To present a run-time scalable hardware-based implementation of a lossless hyperspectral data compression algorithm using a configurable number of low-complexity compressor cores managed by a DPR-enabled hardware processing architecture on a commercial off-the-shelf device, aiming to achieve adaptive throughput and energy efficiency for space applications.
研究成果
The proposed run-time scalable implementation of the CCSDS 123 standard using ARTICo3 and HyLoC accelerators is competitive with state-of-the-art hyperspectral compressors. It enables dynamic adaptation of throughput and energy efficiency by modifying the number of accelerators, with acceptable impacts on compression rate. This approach is feasible for low-cost space applications like CubeSats, encouraging further research in commercial devices with reconfiguration capabilities.
研究不足
The implementation relies on commercial off-the-shelf devices, which may not be radiation-hardened for space environments. Power consumption is estimated rather than measured directly due to lack of on-board measurement circuitry. The parallelization scheme incurs a reduction in compression rate (up to 30% overhead for small subimages), and memory bandwidth can become a bottleneck when scaling to many accelerators (e.g., with 16 accelerators).
1:Experimental Design and Method Selection:
The study employs a data-parallel execution model using the ARTICo3 framework for dynamic and partial reconfiguration (DPR) of FPGAs. The methodology involves partitioning hyperspectral images into fixed-size subimages for independent compression by multiple HyLoC hardware accelerators, enabling SIMD-like parallel processing.
2:Sample Selection and Data Sources:
Hyperspectral images from calibrated AVIRIS datasets (e.g., with 224 spectral bands and varying spatial dimensions) and other datasets like Indian Pines and Yellowstone Scenes are used. Selection criteria include standard calibration and availability for testing compression rates.
3:List of Experimental Equipment and Materials:
A Zynq MMP development board with an XC7Z100-2FFG900 Zynq-7000 device, FPGA tools (Vivado for synthesis and implementation), and the ARTICo3 toolchain for system integration.
4:Experimental Procedures and Operational Workflow:
The FPGA is configured with the ARTICo3 architecture and multiple HyLoC accelerators. Images are partitioned into subimages (e.g., 224 bands x 8 lines x 8 samples), and compression is performed at a clock frequency of 100 MHz. DPR is used to dynamically change the number of accelerators, and performance metrics (throughput, energy efficiency) are measured.
5:Data Analysis Methods:
Data is analyzed using theoretical calculations (e.g., clock cycles per subimage) and empirical measurements from the FPGA implementation. Statistical comparisons are made with state-of-the-art compressors, and power consumption is estimated using Vivado power estimator.
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