- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2018 IEEE International Conference on RFID Technology & Application (RFID-TA) - Macau, Macao (2018.9.26-2018.9.28)] 2018 IEEE International Conference on RFID Technology & Application (RFID-TA) - Alternatives to current RFID chip set market offerings
摘要： There are a large number of RFID chip sets on the market. These chip sets cover the most widely deployed RFID technologies. These chip sets enable the rapid development of RFID readers as well as the inclusion of RFID into other devices. These market offerings frequently require an ancillary microprocessor to undertake the anti-collision algorithm in conjunction with the RFID chip set. These chip sets largely act simply to provide an RF front end with some encoding, decoding, protocol framing and CRC checking to support the overall activity. This paper presents the current state of the RFID chip set market and argues that these offerings fall short of what is required from a genuine RFID solution-on-chip (SoC). Alternatives, including a genuine RFID SoC and dedicated RFID ASIC implementing anti-collision algorithms are proposed.
关键词： FPGA,Anti-collision,ASIC,VHDL,RFID
更新于2025-09-23 15:22:29
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[IEEE 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Tallinn, Estonia (2018.10.30-2018.10.31)] 2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) - Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride & Logic-Level Power Transistors
摘要： Wide bandgap power semiconductors are key enablers for increasing the power density of switch-mode power supplies. However, they require new gate drive technologies. This paper examines and characterizes a fabricated gate-driver in a class-E resonant inverter. The gate-driver’s total area of 1.2 mm2 includes two high-voltage transistors for gate-driving, integrated complementary metal-oxide-semiconductor (CMOS) gate-drivers, high-speed floating level-shifter and reset circuitry. A prototype printed circuit board (PCB) was designed to assess the implications of an electrostatic discharge (ESD) diode, its parasitic capacitance and package bondwire connections. The parasitic capacitance was estimated using its discharge time from an initial voltage and the capacitance is 56.7 pF. Both bondwires and the diode’s parasitic capacitance is neglegible. The gate-driver’s functional behaviour is validated using a parallel LC resonant tank resembling a self-oscillating gate-drive. Measurements and simulations show the ESD diode clamps the output voltage to a minimum of ?2 V.
关键词： Self-oscillating,Analog integrated circuit,gate-driver,ASIC
更新于2025-09-23 15:22:29
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Industrial Production and Field Evaluation of Transparent Electrodynamic Screen (EDS) Film for Water-Free Cleaning of Solar Collectors
摘要： Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore’s Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ‘‘Ages’’ in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.
关键词： commercialization,programmable logic,Moore’s Law,Application-specific integrated circuit (ASIC),economies of scale,field-programmable gate array (FPGA),industrial economics
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Sub-stochiometric MoO <sub/>3</sub> for intermediate band solar cells
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： Scalable systolic arrays,?nite ?eld inversion,ultra-low power devices,hardware security,ASIC
更新于2025-09-23 15:19:57
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Empty Substrate Integrated Waveguide Fed Patch Antenna Array for 5G mm-Wave Communication Systems
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： ?nite ?eld inversion,Scalable systolic arrays,ASIC,ultra-low power devices,hardware security
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Sozopol, Bulgaria (2019.9.6-2019.9.8)] 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Machining Error Influnce on Stress State of Conical Thread Joint Details
摘要： This paper proposes a novel scalable digit-serial inverter structure with low space complexity to perform inversion operation in GF(2m) based on a previously modi?ed extended Euclidean algorithm. This structure is suitable for ?xed size processor that only reuse the core and does not require to modulate the core size when m modi?ed. This structure is extracted by applying a nonlinear methodology that gives the designer more ?exibility to control the processing element workload and also reduces the overhead of communication between processing elements. Implementation results of the proposed scalable design and previously reported ef?cient designs show that the proposed scalable structure achieves a signi?cant reduction in the area ranging from 83.0% to 88.3% and also achieves a signi?cant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them. This makes the proposed design more suitable for constrained implementations of cryptographic primitives in ultra-low power devices such as wireless sensor nodes and radio frequency identi?cation (RFID) devices.
关键词： ?nite ?eld inversion,Scalable systolic arrays,ASIC,ultra-low power devices,hardware security
更新于2025-09-19 17:13:59
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Front-end ASIC for germanium strip detectors
摘要： The characteristics of a recently developed front-end application specific integrated circuit (ASIC) designed for high-purity germanium (HPGe) strip detectors are detailed. The ASIC contains 32 channels, and can instrument either cathode or anode signals from the HPGe detector. The channels provide low-noise charge amplification, four shaping times, four gain ranges, trimmable discrimination for each channel, time to analog output, and peak detectors with analog memory. The channels process events in parallel, and the ASIC emits a logical-OR of the internal discriminators for external control. Each channel contains a time-to-analog circuit to allow the depth of interaction in a detector to be determined. The ASIC has a small noise slope, allowing it to maintain germanium energy resolution at the large, 30 pF, input capacitance of a germanium strip detector connected through the cryostat by a kapton flex cable. The ASIC sparsifies the triggered channels for low deadtime readout. Each channel dissipates 6.2 mW and covers an energy range up to 4 MeV in HPGe. Measurements demonstrate an equivalent noise charge (ENC) of 260 electrons at an input capacitance of 32.5 pF with a slope of 6.4 electrons/pF for a peaking time of 2 μs.
关键词： Gamma ray,Compton,Germanium,HPGe,ASIC
更新于2025-09-10 09:29:36
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Operation of microchannel plate PMTs with TOFPET multichannel timing electronics
摘要： We describe an experimental programme to evaluate TOFPET multichannel timing electronics using microchannel plate PMTs in single photon counting mode. Time resolution measurements were made using: (i) the on-board electronic stim signal; (ii) a Photek PMT210 high speed single anode MCP photomultiplier detector, and; (iii) imaging with a PMT240MA multi-anode MCP detector using a pixelated multi-layer ceramic readout. Experimental measurements using an electronic stim with the ASIC electronics gave a time resolution of 43 ps rms. Detector timing of the PMT210 detector was evaluated using a 40 ps wide pulsed laser with amplitude walk correction using the time over threshold capability of the TOFPET electronics. Single photon timing resolution of better than 100 ps rms was demonstrated. Furthermore, 256 discrete pixel imaging has been demonstrated by coupling a multi-anode pixelated MCP detector to the TOFPET system.
关键词： MCP,Photomultiplier tube,TOFPET,ASIC,PMT,Microchannel plate,Time of flight,Front-end electronics,FEE
更新于2025-09-09 09:28:46
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[IEEE 48th European Solid-State Device Research Conference (ESSDERC 2018) - Dresden (2018.9.3-2018.9.6)] 2018 48th European Solid-State Device Research Conference (ESSDERC) - Smart Connected Sensors - Enablers for the IoT
摘要： The Internet of Things (IoT) is all about making life simpler and more exciting for consumers by interconnecting the world around them. But how can this promise of the IoT be fulfilled? In the world of IoT, microelectromechanical systems (MEMS) sensors form the backbone of the interface between the user and the multitudes of devices that surround us, such as smartphones, wearables, robots and drones. However, making devices able to sense and be connected is simply not enough to realize the grand promise of the IoT. The fact remains, that IoT will only be successful if it follows a user-centric approach, i.e. by solving real-life everyday challenges, making life simpler, enhancing ease of use. Furthermore, ubiquitous sensing of everything on all manner of devices in an ever-increasing number of complex environments poses definite and growing challenges for sensor providers. On ASIC and MEMS development level, these challenges do translate to a significant spread of requirements for multi-platform application approaches by enhancing classical key performance indicators as very high signal evaluation performance or ultra-low power consumption on one side, but also adding new architectures for smart sensor signal fusion or connectivity in arbitrary application use modes on the other side. The continuing rise of complexity due to future IoT market requirements lead to even stronger demand for “first time right” design methodologies in general, and more powerful and effective verification methodologies in particular.
关键词： MEMS sensors,smart connected sensors,connectivity,user-centric approach,signal fusion,IoT,ASIC
更新于2025-09-04 15:30:14
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CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication
摘要： We have been witnessing the continuous size reduction in consumer electronics devices with longer battery life. The Application Specific Integrated Circuits allow for integration of multiple electronics devices on the same dice. At the same time optimizing the transistor and device area lowers power consumption. It is a big challenge to develop such semiconductor processes and also to develop methodologies to monitor the process during semiconductor fabrication. After every major fabrication process, the wafer undergoes an inspection to detect any abnormality that may cause chip failure down the line. An optical inspection using Ultra Violet or Deep Ultra Violet light is designed to find the physical defects that might be “visible” on the wafer. In order to find electrical connection failure during fabrication, a separate approach of electron beam inspection is designed for monitoring metallization processes. In this study, we have used Computer Aided Design layout analysis to guide the defect inspection for both optical and electron beam wafer inspections. The goal was to increase the chances of finding critical defects as well as to reduce the cycle time for the inspection and defect characterization. The proposed approach has been compared with the existing baseline inspection results on the same wafer.
关键词： design optimization,DFM,IC manufacturing,pattern defects,ASIC,wafer inspection
更新于2025-09-04 15:30:14