- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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[IEEE 2018 10th International Conference on Wireless Communications and Signal Processing (WCSP) - Hangzhou, China (2018.10.18-2018.10.20)] 2018 10th International Conference on Wireless Communications and Signal Processing (WCSP) - A Hybrid Decoding Algorithm for Low-Rate LDPC codes in 5G
摘要： A hybrid decoding algorithm for low-density parity-check codes is presented. The proposed algorithm applies different updating schemes, such as the normalized min-sum (NMS) simplification and linear approximation, to the check-node based on its degree. Meanwhile, to eliminate the dependence on the channel variance estimation, the proposed algorithm adopts a multiplicative factor to initialize the channel input and a fixed linear functions for check-node updating. From the iterative thresholds and decoding simulations, our proposed algorithm can be shown to achieve improved performance (much closer to that of the belief propagation decoding) at the expense of a slight increase in complexity to NMS algorithm.
关键词： LDPC codes,iterative decoding,low rate LDPC codes,hybrid decoding
更新于2025-09-23 15:23:52
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Rate-compatible QC-LDPC codes based on PEXIT
摘要： An improved extension method based on protograph extrinsic information transfer (PEXIT) charts is proposed to design rate-compatible quasi-cyclic low-density parity-check (QC-LDPC) codes with more ?exible rates and better performance. The masking matrix of the highest-rate code can ?rst be constructed column by column to own the lowest decoding threshold. Then, an extension algorithm is proposed to obtain the masking matrices of lower-rate codes with ?exible rates. Finally, the base matrices with small amount of short cycles are designed and the parity-check matrices of rate-compatible QC-LDPC codes are obtained through matrix extension. Simulations show that compared with the existing codes, the proposed codes have more ?exible rates while achieving better performance.
关键词： masking matrix,rate-compatible,PEXIT,decoding threshold,QC-LDPC codes
更新于2025-09-23 15:21:21
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Opportunities for High Efficiency Monochromatic Photovoltaic Power Conversion at 1310 nm
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Kolkata, India (2019.8.29-2019.8.31)] 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Effect of I Shaped Periodic Structures over Collinear Arms of 150 Degree Bend Substrate Integrated Waveguide
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Beijing, China (2019.11.21-2019.11.23)] 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Accurate Short-term Forecasting for Photovoltaic Power Method Using RBM Combined LSTM-RNN Structure with Weather Factors Quantification
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Methodology for Predicting Flexible Photovoltaic Cell Life using Accelerated Tests
摘要： Low-density parity-check (LDPC) codes with very long block lengths are well known for their powerful error correction, but it is not always desirable to employ long codes in communication systems, where latency is a serious issue, such as voice and video communication between multiple users. Finite length analyses of LDPC codes have already been presented in the literature for the additive white Gaussian noise channel, but in this paper, we consider the finite length analysis of LDPC codes for channels that exhibit impulsive noise. First, an exact uncoded bit error probability (BEP) of an impulsive noise channel, modeled as a symmetric α-stable (SαS) distribution, is derived. Then, to obtain the LDPC-coded performance, density evolution is applied to evaluate the asymptotic performance of LDPC codes on SαS channels and determine the threshold signal-to-noise ratio. Finally, we derive closed-form expressions for the BEP and block error probability of short LDPC codes on these channels, which are shown to match closely with simulated results on channels with different levels of impulsiveness, even for block lengths as low as 1000 b.
关键词： impulsive noise,density evolution,finite length analysis,LDPC codes
更新于2025-09-23 15:19:57
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[IEEE 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Xiamen, China (2019.12.17-2019.12.20)] 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Microwave Approach to Study Resonant Features of All-dielectric Metasurfaces
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Theoretical study of the MAPbI <sub/>3</sub> /SnO <sub/>2</sub> interface band offset in perovskite solar cells considering mobile ions
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Flexible silicon heterojunction solar cells on 40 ?μm thin substrates
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59
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High Sensitivity Terahertz Biosensor Based on Goos-H?¤nchen Effect in Graphene
摘要： Low-density parity-check (LDPC) codes with very long block lengths are well known for their powerful error correction, but it is not always desirable to employ long codes in communication systems, where latency is a serious issue, such as voice and video communication between multiple users. Finite length analyses of LDPC codes have already been presented in the literature for the additive white Gaussian noise channel, but in this paper, we consider the finite length analysis of LDPC codes for channels that exhibit impulsive noise. First, an exact uncoded bit error probability (BEP) of an impulsive noise channel, modeled as a symmetric α-stable (SαS) distribution, is derived. Then, to obtain the LDPC-coded performance, density evolution is applied to evaluate the asymptotic performance of LDPC codes on SαS channels and determine the threshold signal-to-noise ratio. Finally, we derive closed-form expressions for the BEP and block error probability of short LDPC codes on these channels, which are shown to match closely with simulated results on channels with different levels of impulsiveness, even for block lengths as low as 1000 b.
关键词： impulsive noise,density evolution,finite length analysis,LDPC codes
更新于2025-09-19 17:13:59