- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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A 65 nm 19.1-to-20.4 GHz Sigma-Delta Fractional-N Frequency Synthesizer with Two-Point Modulation for FMCW Radar Applications
摘要： A 19.1-to-20.4 GHz sigma-delta fractional-N frequency synthesizer with two-point modulation (TPM) for frequency modulated continuous wave (FMCW) radar applications is presented. The FMCW synthesizer proposes a digital and voltage controlled oscillator (D/VCO) with large continuous frequency tuning range and small digital controlled oscillator (DCO) gain variation to support TPM. By using TPM technique, it avoids the correlation between loop bandwidth and chirp slope, which is beneficial to fast chirp, phase noise and linearity. The start frequency, bandwidth and slope of the FMCW signal are all reconfigurable independently. The FMCW synthesizer achieves a measured phase noise of ?93.32 dBc/Hz at 1MHz offset from a 19.25 GHz carrier and less than 10 μs locking time. The root-mean-square (RMS) frequency error is only 112 kHz with 94 kHz/μs chirp slope, and 761 kHz with a fast slope of 9.725 MHz/μs respectively. Implemented in 65 nm CMOS process, the synthesizer consumes 74.3 mW with output buffer.
关键词： FMCW radar,fractional-N,two-point modulation,CMOS,phase locked loop,frequency synthesizer
更新于2025-09-23 15:22:29
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An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
摘要： An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.
关键词： on-chip monitoring circuit,sub-sampling,chip-to-chip interface,analog-to-digital converter,phase-locked loop-based frequency synthesizer
更新于2025-09-23 15:22:29
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An Improved Frequency Measurement Method from the Digital PLL Structure for Single-Phase Grid-Connected PV Applications
摘要： The Phase Locked Loop (PLL) technique has been studied to obtain the phase and frequency information in grid-connected distributed generations for the sake of synchronizing the grid voltage and the inverter output current. In particular, the line frequency information, such as the anti-islanding function, is very important for the grid connection requirement. This paper presents a novel frequency measurement method from the digital PLL control structure for single-phase grid-connected PV applications. The conventional PLL controller uses the phase information to calculate the frequency of PV inverter output voltage after every line cycle and has shown a relatively low accuracy. This paper uses the angular frequency to directly measure the frequency after every line cycle. To verify the validity of the proposed method compared with the conventional method, a simulation was conducted. According to the simulation results, the measurement error of the proposed method is 80 times lower than the conventional one.
关键词： phase locked loop,frequency measurement,photovoltaic generation,grid-connection,PV inverter
更新于2025-09-23 15:21:01
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Heterodyne interferometry at ultra-high frequencies with frequency-offset-locked semiconductor lasers
摘要： Modern broadband telecommunications require microelectromechanical filters which mechanically vibrate at ultra-high frequencies up to several gigahertz. Heterodyne interferometers, so-called laser-Doppler vibrometers (LDVs), provide a sensitive and contactless measurement technique for vibrations in such filters, but are limited in GHz heterodyning by the efficiency drop of acousto-optic frequency shifting. Heterodyning by frequency-offset locking of two lasers in an optoelectronic phase-locked loop (OPLL) overcomes this limitation. This is demonstrated with our LDV setup with heterodyning up to 1.4 GHz via offset locking of two semiconductor lasers at visible wavelength. The experiments show a vibration-amplitude resolution of less than 1 pm Hz for frequencies higher than 50 MHz up to 700 MHz. The bandwidth is only per limited by our photodetectors. This amplitude resolution already qualifies our LDV for vibration measurement of microelectromechanical filters at ultra-high frequencies. We present a comprehensive model for the vibration-amplitude resolution of a LDV with this technique including the laser linewidths, the OPLL transfer function, and interferometer delays. The experiments with our LDV validate the model predictions from numerical simulations. Finally, we discuss the collapse of the heterodyne carrier at vanishing mutual coherence due to interferometer delays, the transition to shot-noise-limited detection, and provide design recommendations.
关键词： MEMS testing,Vibration measurement,Optical phase-locked loop,Heterodyne interferometry
更新于2025-09-23 15:19:57
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Autonomous Path Planning by Unmanned Aerial Vehicle (UAV) for Precise Monitoring of Large-Scale PV plants
摘要： This paper presents a 3.6 GHz low-noise fractional-N digital phase-locked loop (PLL) that achieves low in-band phase noise. Phase detection is carried out by a proposed 10-bit, 0.8 ps resolution time-to-digital converter (TDC) using a charge pump and a successive-approximation-register analog-to-digital converter (SAR-ADC) with low power and small area. The latency of the TDC is addressed by the designed building blocks. The fractional spurs are reduced by dual-loop least-mean-square (LMS) calibration. A (cid:2)(cid:3)-less and MOS varactor-less LC digitally-controlled oscillator (DCO) is proposed whose frequency resolution is enhanced to 7 kHz (or a unit variable capacitance of 2.6 aF) using a bridging capacitor technique. A prototype chip is fabricated using a 65 nm CMOS process, occupying an active area of 0.38 mm2 and consuming a power of 9.7 mW at a reference frequency of 50 MHz. The measured in-band phase noise is 107.8 dBc/Hz to 110.0 dBc/Hz with a loop bandwidth of 1 to 5 MHz.
关键词： digitally controlled oscillator (DCO),least-mean-square (LMS),digital phase-locked-loop (PLL),time-to-digital converter (TDC),successive-approximation-register analog-to-digital converter (SAR-ADC),frequency synthesizer,CMOS,sub-picosecond resolution
更新于2025-09-23 15:19:57
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[IEEE 2018 International Conference on Smart Grid and Clean Energy Technologies (ICSGCE) - Sg. Long, Cheras, Kajang, Malaysia (2018.5.29-2018.6.1)] 2018 International Conference on Smart Grid and Clean Energy Technologies (ICSGCE) - A Novel Five-Level Inverter Topology with Reactive Power Control for Grid-Connected PV System
摘要： These days multilevel inverters are more popular for grid-connected photovoltaic (PV) systems due to their low cost and high efficiency, as they effectively reduce total harmonic distortion (THD) and electromagnetic interference which results leakage current. Traditional multi-level inverters can only inject real power that cannot provide quality output power. A new international standard VDE-AR-N4105 states that for a grid tied inverter of power rating below 3.68kVA, a power factor (PF) of 0.95 leading to 0.95 lagging should be achieved. So, in this paper the proposed five-level inverter topology for grid-tie PV is controlled using a reactive power control method that ensures higher efficiency while enhancing the stability of the system. The proposed closed loop reactive power control technique additionally provides the ability to inject reactive power into the system. In this proposed topology the reactive power flow standard of operation is explained in details in relation to the proposed multi-level inverter topology. To validate the accuracy of the theoretical analysis, the control technique was applied to the existing multi-level inverter topology and then has been simulated in MATLAB/Simulink software. Comparisons were done on the basis of using and not using PLL for the existing multilevel topology and it is found that, synchronization is achieved with current and voltage if PLL is used, as a result PF is maintained close to unity whereas without PLL the PF decreases. Moreover the five-level output provides a much better output and better PF then other existing topologies.
关键词： phase-locked loop (PLL),multi-level inverters,solar PV,reactive power control
更新于2025-09-23 15:19:57
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Technological Features of Graphene-based RF NEMS Capacitive Switches on a Semi-insulating Substrate
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - A Compact Octa-band Antenna for Handsets Application
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： sub-sampling,analog-to-digital converter (ADC),voltage-domain,All-digital phase-locked loop (AD-PLL),frequency synthesizer,CMOS,low-power
更新于2025-09-19 17:13:59
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[IEEE 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - Tehran, Iran (2018.12.18-2018.12.20)] 2018 Fifth International Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT) - MMWaTT 2018 Organizing Committee
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： frequency synthesizer,sub-sampling,CMOS,voltage-domain,analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),low-power
更新于2025-09-19 17:13:59
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[IEEE 2019 Photonics North (PN) - Quebec City, QC, Canada (2019.5.21-2019.5.23)] 2019 Photonics North (PN) - Differences between foetal and adult meniscus and cartilage revealed by Polarization Second Harmonic Generation Microscopy
摘要： This paper presents an all-digital phase-locked loop (AD-PLL) using a voltage-domain digitization realized by an analog-to-digital converter (ADC) instead of adopting a traditional time-to-digital converter (TDC) which usually suffers from a tradeoff in resolution and power consumption. It consists of an 18 bit class-C digitally controlled oscillator (DCO), a 4 bit comparator, a digital loop filter (DLF), and a frequency-locked loop (FLL). Implemented in 65 nm CMOS technology, the proposed PLL reaches an in-band phase noise of ?112 dBc/Hz and an RMS jitter of 380 fs at a carrier frequency of 2.2 GHz. A figure of merit (FoM) of ?242 dB was achieved with a power consumption of only 4.2 mW.
关键词： analog-to-digital converter (ADC),All-digital phase-locked loop (AD-PLL),voltage-domain,sub-sampling,frequency synthesizer,low-power,CMOS
更新于2025-09-19 17:13:59