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Sub-micron features from polymer-derived SiOC via imprint lithography
摘要： Silicon oxycarbide (SiOC) is a unique class of materials with great potential for facile manufacturing of complex shaped high temperature parts and devices. In this study, we examine the characteristics of micron-sized ridge and rod patterns of SiOC created by imprint lithography. Feature fidelity, shape change, and shrinkage are studied as a function of pyrolysis condition and feature size. All the features have acceptable surface fidelity under the pyrolysis conditions studied. However, pronounced rounding and flattening of patterned features are observed as the pyrolysis temperature increases or the feature size decreases. Based on the Kelvin and Gibbs-Thomson equations, we can predict the feature evolution and show that the feature rounding and flattening are due to surface diffusion and evaporation-condensation. As a result, the features also have more linear shrinkage than the bulk.
关键词： Shrinkage,Feature fidelity,Silicon oxycarbide,Rounding,Pyrolysis
更新于2025-09-23 15:23:52
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[IEEE 2019 9th International Electric Drives Production Conference (EDPC) - Esslingen, Germany (2019.12.3-2019.12.4)] 2019 9th International Electric Drives Production Conference (EDPC) - Fault Classification and Correction based on Convolutional Neural Networks exemplified by laser welding of hairpin windings
摘要： Using parallel associative reduction, iterative re?nement, and conservative early termination detection, we show how to use tree-reduce parallelism to compute correctly rounded ?oating-point sums in Oelog NT depth. Our parallel solution shows how we can continue to exploit the scaling in transistor count to accelerate ?oating-point performance even when clock rates remain ?at. Empirical evidence suggests our iterative algorithm only requires two tree-reduce passes to converge to the accurate sum in virtually all cases. Furthermore, we develop the hardware implementation of two residue-preserving IEEE-754 double-precision ?oating-point adders on a Virtex 6 FPGA that run at the same 250 MHz pipeline speed as a standard adder. One adder creates the residue by truncation, requires only 22 percent more area than the standard adder, and allows us to support directed-rounding modes and to lower the cost of round-to-nearest modes. The second adder creates the residue while directly producing a round-to-nearest sum at 48 percent more area than a standard adder.
关键词： accuracy,accumulation,IEEE-754,Floating-point arithmetic,parallel,FPGA,correct rounding
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Analysis of ARMA Solar Forecasting Models Using Ground Measurements and Satellite Images
摘要： Using parallel associative reduction, iterative re?nement, and conservative early termination detection, we show how to use tree-reduce parallelism to compute correctly rounded ?oating-point sums in Oelog NT depth. Our parallel solution shows how we can continue to exploit the scaling in transistor count to accelerate ?oating-point performance even when clock rates remain ?at. Empirical evidence suggests our iterative algorithm only requires two tree-reduce passes to converge to the accurate sum in virtually all cases. Furthermore, we develop the hardware implementation of two residue-preserving IEEE-754 double-precision ?oating-point adders on a Virtex 6 FPGA that run at the same 250 MHz pipeline speed as a standard adder. One adder creates the residue by truncation, requires only 22 percent more area than the standard adder, and allows us to support directed-rounding modes and to lower the cost of round-to-nearest modes. The second adder creates the residue while directly producing a round-to-nearest sum at 48 percent more area than a standard adder.
关键词： Floating-point arithmetic,accumulation,IEEE-754,parallel,accuracy,correct rounding,FPGA
更新于2025-09-19 17:13:59