- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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A geometric partitioning method for distributed tomographic reconstruction
摘要： Tomography is a powerful technique for 3D imaging of the interior of an object. With the growing sizes of typical tomographic datasets, the computational requirements for algorithms in tomography are rapidly increasing. Parallel and distributed-memory methods for tomographic reconstruction are therefore becoming increasingly common. An under-exposed aspect is the effect of the data distribution on the performance of distributed-memory reconstruction algorithms. In this work, we introduce a geometric partitioning method, which takes into account the acquisition geometry and aims to minimize the necessary communication between nodes for distributed-memory forward projection and backprojection operations. These operations are crucial subroutines for an important class of reconstruction methods. We show that the choice of data distribution has a significant impact on the runtime of these methods. With our novel partitioning method we reduce the communication volume drastically compared to straightforward distributions, by up to 90% for a number of cases, and furthermore we guarantee a specified load balance.
关键词： sparse matrix,tomography,matrix partitioning,parallel computing
更新于2025-09-23 15:23:52
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A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing
摘要： This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16 × 16 pixel array (or 64 × 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip.
关键词： parallel computing,imager,3-D stacking,vision chip
更新于2025-09-23 15:22:29
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A fast reconstruction method for three-dimensional shape measurement using dual-frequency grating projection and phase-to-height lookup table
摘要： Phase-to-height mapping is indispensable part of three-dimensional (3D) shape measurement system based on phase analysis, which guarantees the accuracy of 3D reconstruction. In this paper, a fast 3D shape reconstruction method based on dual-frequency grating projection and phase-to-height lookup table is proposed. In this proposed method, the reference plane is moved with known interval along the measurement depth direction to establish the mapping lookup table between the phase of the high and low frequency projected grating and their corresponding spatial height pixel by pixel respectively. Then, two methods to establish the lookup table with the unwrapped and the wrapped phase have been respectively introduced according to the characteristics of dual-frequency grating. The actual experimental results show that the two methods can effectively extend the measurement range of the current wrapped phase-to-height lookup method, and the reconstruction accuracy is better than the traditional phase-to-height quadratic fitting method. At the same time, the consumed time for 3D shape reconstruction of the tested object by the two methods is compared and analyzed. Finally, combining the high performance parallel computation of GPU, the fast 3D shape reconstruction is realized with the speed of 60fps.
关键词： Dual-frequency grating,Parallel computing,3D shape measurement,Multi-reference plane,Phase-to-height mapping
更新于2025-09-23 15:22:29
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High Resolution and Fast Processing of Spectral Reconstruction in Fourier Transform Imaging Spectroscopy
摘要： High-resolution spectrum estimation has continually attracted great attention in spectrum reconstruction based on Fourier transform imaging spectroscopy (FTIS). In this paper, a parallel solution for interference data processing using high-resolution spectrum estimation is proposed to reconstruct the spectrum in a fast high-resolution way. In batch processing, we use high-performance parallel-computing on the graphics processing unit (GPU) for higher efficiency and lower operation time. In addition, a parallel processing mechanism is designed for our parallel algorithm to obtain higher performance. At the same time, other solving algorithms for the modern spectrum estimation model are introduced for discussion and comparison. We compare traditional high-resolution solving algorithms running on the central processing unit (CPU) and the parallel algorithm on the GPU for processing the interferogram. The experimental results illustrate that runtime is reduced by about 70% using our parallel solution, and the GPU has a great advantage in processing large data and accelerating applications.
关键词： parallel computing,high performance,GPU,Fourier transform imaging spectrometer,spectrum reconstruction
更新于2025-09-23 15:22:29
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Run-to-run control of PECVD systems: Application to a multiscale three-dimensional CFD model of silicon thin film deposition
摘要： Deposition of amorphous silicon thin films via plasma-enhanced chemical vapor deposition (PECVD) and batch-to-batch operation under run-to-run control of the associated chambered reactor are presented in this work using a recently developed multiscale, three-dimensional in space, computational fluid dynamics model. Macroscopic reactor scale behaviors are linked to the microscopic growth of amorphous silicon thin films using a dynamic boundary which is updated at each time step of the transient in-batch simulations. This novel workflow is distributed across 64 parallel computation nodes in order to reduce the significant computational demands of batch-to-batch operation and to allow for the application and evaluation in both radial and azimuthal directions across the wafer of a benchmark, run-to-run based control strategy. Using 10 successive batch deposition cycles, the exponentially weighted moving average algorithm, an industrial standard, is demonstrated to drive all wafer regions to within 1% of the desired thickness set-point in both radial and azimuthal directions across the wafer surface. This is the first demonstration of run-to-run control in reducing azimuthal film nonuniformity. Additionally, thin film uniformity is shown to be improved for poorly optimized PECVD geometries by manipulating the substrate temperature alone, without the need for re-tooling of the equipment.
关键词： thin film silicon solar cells,parallel computing,multiscale modeling,computational fluid dynamics,run-to-run control,thin film growth
更新于2025-09-23 15:21:21
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Opportunities for High Efficiency Monochromatic Photovoltaic Power Conversion at 1310 nm
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Kolkata, India (2019.8.29-2019.8.31)] 2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) - Effect of I Shaped Periodic Structures over Collinear Arms of 150 Degree Bend Substrate Integrated Waveguide
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-23 15:21:01
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[IEEE 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Beijing, China (2019.11.21-2019.11.23)] 2019 IEEE Sustainable Power and Energy Conference (iSPEC) - Accurate Short-term Forecasting for Photovoltaic Power Method Using RBM Combined LSTM-RNN Structure with Weather Factors Quantification
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-23 15:19:57
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[IEEE 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Xiamen, China (2019.12.17-2019.12.20)] 2019 Photonics & Electromagnetics Research Symposium - Fall (PIERS - Fall) - Microwave Approach to Study Resonant Features of All-dielectric Metasurfaces
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： parallel computing,GPU,LDPC decoders,reconfigurable computing,high-level synthesis,CPU,LDPC codes
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Theoretical study of the MAPbI <sub/>3</sub> /SnO <sub/>2</sub> interface band offset in perovskite solar cells considering mobile ions
摘要： Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity-approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with the ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions has shown that multicore and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. This paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.
关键词： LDPC codes,high-level synthesis,CPU,parallel computing,LDPC decoders,reconfigurable computing,GPU
更新于2025-09-19 17:13:59