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Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)
摘要： With increasing integration density of three-dimensional ICs, temperature is one of the major concern of circuit design, which influences the performance and reliability. In this paper, the parasitic capacitance of tapered TSV (T-TSV) with respect of thermal properties is studied. The concept of the Temperature Coefficient of Capacitance (TCC) is proposed to model the sensitive of TSV capacitance to temperature. It is found that TSV capacitance is sensitive to temperature under high frequency application, and the MOS capacitance variation is the main reason for the change of TSV capacitance and the TCC increases with elevated temperature. Furthermore, the affections of TSV dimensions on TCC are discussed. It is shown that the TCC increases gradually as the TSV radius increases, while the thickness of dielectric layer is the opposite. The cylinder TSV is less thermal sensitive than tapered TSV. This paper provides basis for TSV design considering the temperature effect.
关键词： tapered through silicon via (T-TSV),parasitic capacitance,temperature effect,three-dimensional ICs (3D ICs)
更新于2025-09-23 15:23:52
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[IEEE 2019 IEEE 10th International Symposium on Power Electronics for Distributed Generation Systems (PEDG) - Xi'an, China (2019.6.3-2019.6.6)] 2019 IEEE 10th International Symposium on Power Electronics for Distributed Generation Systems (PEDG) - An Extraction Method for the Parasitic Capacitance of the Photovoltaic Module Based on the Oscillation of the Leakage Current
摘要： In photovoltaic (PV) plant, the parasitic capacitance between the PV module and the ground causes leakage current in the non-isolated systems. The case can be deteriorated in the rain environment, because increases dramatically due to the rain water. This paper presents an extraction method for the parasitic capacitance between the PV module and the ground. Unlike the common analytical, numerical way and direct measurement method, the parasitic capacitance is obtained through measurement of the leakage current oscillation. A full-bridge inverter is used to explain the principle as well as for the measurement. Theoretical calculation, MATLAB simulations and experimental measurements finally verify the accuracy of the proposed methods. The experimental results are shown to validate the method works well.
关键词： photovoltaic module,parasitic capacitance,leakage current,oscillation
更新于2025-09-11 14:15:04
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Common Mode Noise Reduction of 3-level Active Neutral Point Clamped Inverters with Uncertain Parasitic Capacitance of Photovoltaic Panels
摘要： SiC devices can upgrade the inverter performance to a new level by its potentially more than 10 times higher switching speed compared to its Si counterpart. Whereas, the high switching frequency and dv/dt, di/dt worsen the electromagnetic interference (EMI). Reduction of the common mode (CM) noise of the non-isolated photovoltaic (PV) inverters are addressed by many researchers through adding filters or balancing the circuit. However, most methods rely on the certainty of the parasitics in the system in advance. It is usually not practical for a PV inverter because the parasitic capacitance of PV panels that are to be installed in plants varies from case to case and further can be seriously affected by the damp environment. This paper proposes a practical way to reduce the CM noise of the 3-level (3L) active neutral point clamped (ANPC) inverters with uncertain parasitic capacitance of PV panels. Firstly, the CM model of ANPC inverters with all parasitic capacitances is established. Next, most existing hardware-based reduction methods of the CM noise are summarized based on a unified mathematical model and further compared with each other. After the comparison, a practical method is proposed to reduce the CM noise of the ANPC inverter with uncertain parasitic capacitances, which just adds little volume and cost to the whole system. Finally, the simulation and experiments are conducted to validate the proposed method.
关键词： EMI elimination,common mode (CM),active neutral point clamped (ANPC) topology,electromagnetic interference (EMI),Uncertain parasitic capacitance
更新于2025-09-11 14:15:04
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Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors
摘要： This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal–oxide–semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), and a diode model to simulate a cascode GaN FET, in which a JFET was used to simulate a metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT). Using the JFET to simulate the MIS-HEMT not only ensures that the curve fits an S-shape transfer characteristic but also enables the pinch-off voltages extracted from the threshold voltage of the MIS-HEMT to be used as a watershed to distinguish where the drop in parasitic capacitance occurs. Parameter extraction was based on static and dynamic characteristics, which involved simulating the behavior of the created GaN FET model and comparing the extracted parameters with experimental measurements to demonstrate the accuracy of the simulation program with an integrated circuit emphasis (SPICE) model. Cascode capacitance was analyzed and verified through experimental measurements and SPICE simulations. The analysis revealed that the capacitance of low-voltage MOSFETs plays a critical role in increasing the overall capacitance of cascode GaN FETs. The turn-off resistance mechanism effectively described the leakage current, and a double-pulse tester was used to evaluate the switching performance of the fabricated cascode GaN FET. LTspice simulation software was adopted to compare the experimental switching results. Overall, the simulation results were strongly in agreement with the experimental results.
关键词： turn-off resistance,GaN FET,MIS-HEMT,SPICE,cascode,behavioral model,parasitic capacitance
更新于2025-09-10 09:29:36
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Effects of parasitic capacitance on both static and dynamic electrical characteristics of back-gated two-dimensional semiconductor negative-capacitance field-effect transistors
摘要： Negative-capacitance ?eld-e?ect transistors (NC-FETs) are a promising candidate for future low-power Internet of Things (IoT) applications. In this work, a uni?ed analytical drain-current model for back-gated two-dimensional (2D) NC-FETs has been proposed for both static and dynamic is calibrated to experimental data. E?ects of parasitic capacitance on both the static and dynamic electrical simulations, and this model characteristics of back-gated 2D NC-FETs are investigated systematically on the basis of the model. It is found that parasitic capacitance contributes to the reduction in subthreshold swing but leads to a larger dynamic hysteresis. Thus, a balance between both should be carefully taken into account.
关键词： Negative-capacitance ?eld-e?ect transistors,NC-FETs,dynamic hysteresis,subthreshold swing,parasitic capacitance
更新于2025-09-09 09:28:46
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Analysis of transformer less inverter for PV applications
摘要： To enhance the effectiveness and decrease the cost of a Photovoltaic (PV) system, the utilization of transformer less PV inverters is an option of expanding interest. In any case, this topology should be considered in detail, as it shows a few issues like effectiveness degradation and safety issues identified with the galvanic association between the system and the PV generator. In this research paper, a review of standalone and grid-connected PV inverter structures has been done. From one viewpoint, a few options in light of established structures have been introduced. At last parasitic capacitance in PV arrays and leakage current produced from PV systems are examined.
关键词： Grid Connected Systems,Parasitic Capacitance,Leakage Current,Photovoltaic,Transformer Less Inverters
更新于2025-09-04 15:30:14