- 标题
- 摘要
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- 实验方案
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[IEEE 2018 IEEE Power & Energy Society General Meeting (PESGM) - Portland, OR, USA (2018.8.5-2018.8.10)] 2018 IEEE Power & Energy Society General Meeting (PESGM) - Experimental Determination of PV Inverter Response to Grid Phase Shift Events
摘要： With the continued growth of renewable energy resources which interface to the electric grid via inverters, the understanding of such devices becomes ever more important to the safe and reliable operation of the bulk power system. This work investigates the specific response of a utility-scale PV inverter to grid voltage phase shift-type disturbances which sometimes occur during grid fault events. The role of the PV inverter’s phase-locked-loop (PLL) is identified as important to modeling the response. Switching-level simulations of a utility-scale PV inverter with a modeled PLL show a characteristic response when phase shift disturbances require the PLL to track what appear as fast frequency changes. Additionally, in this work a full-scale laboratory testing was carried out using the Opal real time (RT) OP5142 real time simulator and a large grid simulator to create phase shift disturbances with a high degree of repeatability. A photovoltaic (PV) inverter was connected to a grid simulator, and phase shifts were instantaneously implemented on the simulated grid, the results of the currents were then obtained. The experimental results obtained were validated with simulation results obtained from MATLAB/Simulink.
关键词： frequency response,photovoltaics,phase-locked loops,harmonics,inverter,DER
更新于2025-09-23 15:23:52
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[IEEE 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Tainan, Taiwan (2018.11.5-2018.11.7)] 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization
摘要： A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm2.
关键词： phase noise,tracking loops,CMOS integrated circuits,radio frequency,phase locked loops,phased-arrays,delay-lines
更新于2025-09-23 15:22:29
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Design and performance analysis of improved Adaline technique for synchronization and load compensation of grida??tied photovoltaic system
摘要： The paper discusses the design, modeling, simulation, and implementation of improved Adaline technique, which has been used for grid synchronization as well as extended further for load compensation. A simple but effective method is proposed to improve the performance of the conventional Adaline technique. The conventional Adaline controller uses a fixed learning rate while the proposed Adaline is developed using variable learning, which improves both the steady-state and dynamic response. Simulation and experimental results have been demonstrated, which confirm the feasibility of the proposed approach. Suitable performance comparisons highlight the effectiveness of the proposed approach.
关键词： power quality,ANN,phase-locked loops,synchronization,harmonic distortion
更新于2025-09-19 17:13:59
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Grid-Connected Photovoltaic Power Plant without Phase Angle Synchronization Able to Address Fault Ride-Through Capability
摘要： This paper discusses the control of large-scale grid-connected photovoltaic power plants (GCPPPs) operating under unbalanced grid voltage sags. The positive and negative sequences of the output currents are controlled to achieve different targets: injecting constant power (i) to the grid, or (ii) to the ac side of the converter, i.e., including the filter and the grid. Traditionally, synchronization with the grid voltages is required, which is usually performed by a phase-locked-loop (PLL) technique. In this paper, the proposed control technique does not require any grid voltage synchronization. An arbitrary angle is used instead with the only requirement of having a frequency equal or close to the grid frequency. The fault-ride-through capability of the GCPPP during unbalanced voltage sags is addressed by proposing a current limiter. Simulation and experimental results verify the performance of the proposed GCPPP.
关键词： Power system faults,Phase locked loops,Photovoltaic systems,Fault current limiters
更新于2025-09-11 14:15:04
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[IEEE 2018 15th European Radar Conference (EuRAD) - Madrid, Spain (2018.9.26-2018.9.28)] 2018 15th European Radar Conference (EuRAD) - A Highly Integrated Dual Band FMCW Radar Receiver for Indoor Positioning Applications
摘要： This work presents the design of a highly integrated dual band frequency modulated continuous wave (FMCW) radar receiver (RX) at the 2.4 and 5.8 GHz industrial, scientific and medical bands. As opposed to earlier versions of this work, baseband low pass filtering is performed by the integrated variable gain amplifier (VGA) thus eliminating the need for an off-chip low pass filter (LPF) together with the required chip pads needed for this external filter. Fabricated on an IBM 0.18 μm BiCMOS process as part of a dual band FMCW radar transceiver (TRX), the measured RX performance is in good agreement with simulations and measurements from previous RX versions with the external LPF achieving a dynamic range of more than 50 dB and a baseband signal-to-noise ratio (SNR) of around 18 dB at -70 dBm radio frequency (RF) input power and an input-referred 3rd order intercept point (IIP3) of around -7 dBm. To the best of the author’s knowledge, with a chip area of 2.4 mm2, this filterless dual band FMCW radar TRX has the highest level of integration reported in the literature.
关键词： radar,receivers,Amplifiers,gain control,mixers,filters,phase locked loops
更新于2025-09-04 15:30:14