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[IEEE 2018 XIV International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE) - Novosibirsk, Russia (2018.10.2-2018.10.6)] 2018 XIV International Scientific-Technical Conference on Actual Problems of Electronics Instrument Engineering (APEIE) - Universal Control System of a Semiconductor Electric Energy Converter on Programmable Logic Devises
摘要： The article presents the results of the development of a universal control system for semiconductor power converters based on a programmable logic devices (PLD). As a result of the work done, shared functional modules for the various control systems of semiconductor converters were determined, the features of implementing modules on programmable logic were considered, and the algorithms for controlling converters on mathematical models were studied. The principal circuit diagram of the universal control system of the converter is synthesized on the basis of a combination of programmable logic devises and a microcontroller. The topologies of printed circuit boards and their layout in a single module of the universal control system of the converter are developed; the built-in microcontroller software was written and debugged in the assembler language. An experimental sample of the control system was made and its joint tests with a prototype of a low-power three-phase inverter equipped with a load simulator were carried out, oscillograms of control pulses and output voltage were obtained in various modes of inverter control.
关键词： digital control system,programmable logic device,algorithm,semiconductor power converter,model
更新于2025-09-23 15:23:52
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Industrial Production and Field Evaluation of Transparent Electrodynamic Screen (EDS) Film for Water-Free Cleaning of Solar Collectors
摘要： Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore’s Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed ‘‘Ages’’ in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.
关键词： commercialization,programmable logic,Moore’s Law,Application-specific integrated circuit (ASIC),economies of scale,field-programmable gate array (FPGA),industrial economics
更新于2025-09-23 15:19:57
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[IEEE 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC) - Fukuoka, Japan (2019.7.7-2019.7.11)] 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC) - High-speed RF interconnects beyond 67 GHz in InP photonic integration technology
摘要： Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON). The ECHELON technique utilizes analog evolved building blocks and refines their output using digital fabric to compose power series expansions of transcendental functions which are all routed under intrinsic control on a field-programmable SoC (PSoC). The result for the evolution of seven different powers of the independent variable is a reduction of 31.24% in the overall error as compared to the analog circuits that produce the raw inputs to a differential digital correction phase. Computation blocks developed on a Cypress PSoC-5LP mixed-signal SoC reduced error in the final mathematical approximation to the range of 40–150 mV. In doing so, speedups of roughly 1.4-fold to 6.6-fold with an average of 2.72-fold reduction in function execution times were attained. In particular, this approach achieved a 41.7-fold reduction in error with respect to the largest power of the independent variable used as an input to compute an er(x) function.
关键词： genetic algorithm,programmable logic device,Programmable system on chip (PSoC),power series
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Sozopol, Bulgaria (2019.9.6-2019.9.8)] 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Airy Pulse Transformation by an Accelerated Medium Boundary
摘要： Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON). The ECHELON technique utilizes analog evolved building blocks and re?nes their output using digital fabric to compose power series expansions of transcendental functions which are all routed under intrinsic control on a ?eld-programmable SoC (PSoC). The result for the evolution of seven different powers of the independent variable is a reduction of 31.24% in the overall error as compared to the analog circuits that produce the raw inputs to a differential digital correction phase. Computation blocks developed on a Cypress PSoC-5LP mixed-signal SoC reduced error in the ?nal mathematical approximation to the range of 40–150 mV. In doing so, speedups of roughly 1.4-fold to 6.6-fold with an average of 2.72-fold reduction in function execution times were attained. In particular, this approach achieved a 41.7-fold reduction in error with respect to the largest power of the independent variable used as an input to compute an er(cid:102)(x) function.
关键词： Programmable system on chip (PSoC),programmable logic device,genetic algorithm,power series
更新于2025-09-19 17:13:59