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Ultraviolet Nanosecond Laser Annealing for Low Temperature 3D-Sequential Integration Gate Stack
摘要： For the top tier in a 3D sequential integration, we propose a low temperature gate first approach in which an in-situ doped amorphous silicon layer is deposited at 475°C then subsequently converted into a polycrystalline film using ultraviolet nanosecond laser annealing. We demonstrate the ability to obtain a low resistance poly-Si gate for the top transistors within a thermal budget expected to preserve the bottom devices electrical performance.
关键词： Ultraviolet Nanosecond Laser Annealing,Polycrystalline Silicon,3D-Sequential Integration,Low Temperature Gate Stack
更新于2025-09-16 10:30:52
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[IEEE 48th European Solid-State Device Research Conference (ESSDERC 2018) - Dresden (2018.9.3-2018.9.6)] 2018 48th European Solid-State Device Research Conference (ESSDERC) - InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance
摘要： In this paper, we demonstrate InGaAs FinFETs 3D sequentially (3DS) integrated on top of a fully-depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. The low thermal budget of the top layer process caused no performance degradation of the lower level FETs. Record ION of 200 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V) for 3DS integrated III-V FETs on silicon is demonstrated, with a 50% reduction of RON compared to previous work. The achieved improved performance can be attributed to the introduction of doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.
关键词： 3DS,monolithic integration,wafer bonding,III-V,sequential integration,FinFETs
更新于2025-09-04 15:30:14