研究目的
Demonstrating InGaAs FinFETs 3D sequentially integrated on top of a fully-depleted silicon-on-insulator CMOS with record performance.
研究成果
The study successfully demonstrates InGaAs FinFETs 3DS integrated on FDSOI Si CMOS with minimal performance degradation in both transistor levels. Record ION of 200 μA/μm is achieved, attributed to improvements in wafer bonding and the introduction of doped extensions. The results show that 3DS integration of III-V FETs on Si CMOS can be performed with minimal performance degradation.
研究不足
The study is limited by the thermal budget management and the integration of channel layers with low defect density. Further scaling of fin width may be necessary to enhance off-state performance and scalability.
1：Experimental Design and Method Selection:
The study involves the sequential fabrication of multiple transistor levels (3DS integration) on a fully-depleted silicon-on-insulator (FDSOI) Si CMOS layer. A Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth are used for the top layer III-V FETs.
2：Sample Selection and Data Sources:
The active device layer is patterned on a silicon-on-insulator (SOI) substrate. A 20 nm In0.53Ga0.47As layer is sequentially integrated on the Si CMOS wafer by direct wafer bonding.
3：53Ga47As layer is sequentially integrated on the Si CMOS wafer by direct wafer bonding.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: Equipment includes electron beam lithography and dry etching for patterning, metal-organic chemical vapor deposition (MOCVD) for n+InGaAs RSD epitaxy, and chemical-mechanical polishing (CMP) for planarization.
4：Experimental Procedures and Operational Workflow:
The process involves gate-first FDSOI fabrication for the bottom Si CMOS layer, followed by the integration of the top III-V layer with a low thermal budget process. Key steps include dummy metal gate deposition, gate patterning, spacer formation, doped extensions, and HK and metal gate deposition.
5：Data Analysis Methods:
Performance metrics such as ION, IOFF, RON, subthreshold slope, and transconductance are analyzed to evaluate the devices.
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