- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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HLS Based Approach to Develop an Implementable HDR Algorithm
摘要： Hardware suitability of an algorithm can only be verified when the algorithm is actually implemented in the hardware. By hardware, we indicate system on chip (SoC) where both processor and field-programmable gate array (FPGA) are available. Our goal is to develop a simple algorithm that can be implemented on hardware where high-level synthesis (HLS) will reduce the tiresome work of manual hardware description language (HDL) optimization. We propose an algorithm to achieve high dynamic range (HDR) image from a single low dynamic range (LDR) image. We use highlight removal technique for this purpose. Our target is to develop parameter free simple algorithm that can be easily implemented on hardware. For this purpose, we use statistical information of the image. While software development is verified with state of the art, the HLS approach confirms that the proposed algorithm is implementable to hardware. The performance of the algorithm is measured using four no-reference metrics. According to the measurement of the structural similarity (SSIM) index metric and peak signal-to-noise ratio (PSNR), hardware simulated output is at least 98.87 percent and 39.90 dB similar to the software simulated output. Our approach is novel and effective in the development of hardware implementable HDR algorithm from a single LDR image using the HLS tool.
关键词： system on chip,high-dynamic range image,low-dynamic range image,field-programmable gate array,high-level synthesis
更新于2025-09-23 15:22:29
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Background Light Rejection in SPAD-Based LiDAR Sensors by Adaptive Photon Coincidence Detection
摘要： Light detection and ranging (LiDAR) systems based on silicon single-photon avalanche diodes (SPAD) offer several advantages, like the fabrication of system-on-chips with a co-integrated detector and dedicated electronics, as well as low cost and high durability due to well-established CMOS technology. On the other hand, silicon-based detectors suffer from high background light in outdoor applications, like advanced driver assistance systems or autonomous driving, due to the limited wavelength range in the infrared spectrum. In this paper we present a novel method based on the adaptive adjustment of photon coincidence detection to suppress the background light and simultaneously improve the dynamic range. A major disadvantage of fixed parameter coincidence detection is the increased dynamic range of the resulting event rate, allowing good measurement performance only at a specific target reflectance. To overcome this limitation we have implemented adaptive photon coincidence detection. In this technique the parameters of the photon coincidence detection are adjusted to the actual measured background light intensity, giving a reduction of the event rate dynamic range and allowing the perception of high dynamic scenes. We present a 192 × 2 pixel CMOS SPAD-based LiDAR sensor utilizing this technique and accompanying outdoor measurements showing the capability of it. In this sensor adaptive photon coincidence detection improves the dynamic range of the measureable target reflectance by over 40 dB.
关键词： system-on-chip (SoC),single-photon avalanche diode (SPAD),CMOS,light detection and ranging (LiDAR),time-of-flight (TOF),background light rejection
更新于2025-09-23 15:22:29
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[IEEE 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Tainan, Taiwan (2018.11.5-2018.11.7)] 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - A 137-μW Area-Efficient Real-Time Gesture Recognition System for Smart Wearable Devices
摘要： Gesture recognition has increasingly become one of the most popular human-machine interaction techniques for smart devices. Existing gesture recognition systems suffer from either excessive power consumption or large size, limiting their applications for ultra-low power IoT and wearable devices. This paper presents an accurate, area-efficient, and ultra-low power real-time gesture recognition system for smart wearable devices. The proposed work utilizes a peak-based gesture classification engine with less memory and a low-resolution and low-power on-chip image sensor for achieving high area efficiency and low power. The feature extraction architecture removes fixed-pattern noises from the low-power on-chip image sensor for accuracy improvement and employs parallelism for recognition speed enhancement. The proposed system requires only 3.2 KB on-chip memory for processing 32x32 pixel data. Measurement results of a test chip fabricated in 65nm CMOS demonstrate that the proposed system consumes 137.0 pW at 0.8 V and 30fps while occupying only 1.78mm2, which achieves the lowest power and smallest area among existing gesture recognition systems.
关键词： system on chip,low power processor,image sensor,wearable devices,gesture recognition,feature extraction
更新于2025-09-23 15:22:29
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[IEEE 2020 Argentine Conference on Electronics (CAE) - Buenos Aires, Argentina (2020.2.27-2020.2.28)] 2020 Argentine Conference on Electronics (CAE) - System-on-Chip Implementation of a Self-Configuration System for a Programmable Photodetector ASIC
摘要： In this work a self-con?guration system for a photodetector sensor with programmable pixels is presented. The design is part of an optical encoder based on a non-diffractive light beam. The self-con?guration is a routine of con?gurations, readings and successive recon?gurations whose main purpose is ?nding the center of the non-diffractive beam incident on the sensor, and then con?gure around it the detection pattern. This algorithm is implemented on a Zynq-7000 SoC and makes it possible to automate the alignment of the beam with the detection pattern, without using micrometric positioning procedures.
关键词： Self-con?guration system,System-On-Chip,FPGA prototyping
更新于2025-09-23 15:21:01
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[IEEE 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC) - Fukuoka, Japan (2019.7.7-2019.7.11)] 2019 24th OptoElectronics and Communications Conference (OECC) and 2019 International Conference on Photonics in Switching and Computing (PSC) - High-speed RF interconnects beyond 67 GHz in InP photonic integration technology
摘要： Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON). The ECHELON technique utilizes analog evolved building blocks and refines their output using digital fabric to compose power series expansions of transcendental functions which are all routed under intrinsic control on a field-programmable SoC (PSoC). The result for the evolution of seven different powers of the independent variable is a reduction of 31.24% in the overall error as compared to the analog circuits that produce the raw inputs to a differential digital correction phase. Computation blocks developed on a Cypress PSoC-5LP mixed-signal SoC reduced error in the final mathematical approximation to the range of 40–150 mV. In doing so, speedups of roughly 1.4-fold to 6.6-fold with an average of 2.72-fold reduction in function execution times were attained. In particular, this approach achieved a 41.7-fold reduction in error with respect to the largest power of the independent variable used as an input to compute an er(x) function.
关键词： genetic algorithm,programmable logic device,Programmable system on chip (PSoC),power series
更新于2025-09-19 17:13:59
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Kapitza Pendulum Effect with Overclocked Raman Comb Solitons in a Microring Resonator
摘要： In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection pulling through parasitic coupling between various LC-tank oscillators as well as between them and strong transmitter (TX) outputs. Any static or dynamic frequency proximity between aggressors (i.e., oscillators and TX outputs) and victims (i.e., oscillators) that share the same die causes injection pulling, which produces unwanted spurs and/or modulation distortion. In this paper, we propose and demonstrate a new frequency planning technique of a multicore TX where each LC-tank oscillator is separated from other aggressors beyond its pulling range. This is done by breaking the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels using digital fractional divider based on a phase rotation. Each oscillator’s center frequency can be fractionally separated by ～28% but, at the same time, both producing closely spaced frequencies at the phase rotator outputs. The injection-pulling spurs are so far away that they are insigni?cantly small (?80 dBc) and coincide with the second harmonic of the carrier. This method is experimentally veri?ed in a two-channel system in 65-nm digital CMOS, each channel comprising a high-swing class-C oscillator, frequency divider, and phase rotator.
关键词： digitally controlled oscillator (DCO),Digital fractional divider,RF-SoC,multi-core radio,frequency pulling,system on chip (SoC),injection locking
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Sozopol, Bulgaria (2019.9.6-2019.9.8)] 2019 IEEE 8th International Conference on Advanced Optoelectronics and Lasers (CAOL) - Airy Pulse Transformation by an Accelerated Medium Boundary
摘要： Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evolutionary approach to realize complex computational circuits called Embedded-Cascaded Hierarchically Evolved Logic Output Networks (ECHELON). The ECHELON technique utilizes analog evolved building blocks and re?nes their output using digital fabric to compose power series expansions of transcendental functions which are all routed under intrinsic control on a ?eld-programmable SoC (PSoC). The result for the evolution of seven different powers of the independent variable is a reduction of 31.24% in the overall error as compared to the analog circuits that produce the raw inputs to a differential digital correction phase. Computation blocks developed on a Cypress PSoC-5LP mixed-signal SoC reduced error in the ?nal mathematical approximation to the range of 40–150 mV. In doing so, speedups of roughly 1.4-fold to 6.6-fold with an average of 2.72-fold reduction in function execution times were attained. In particular, this approach achieved a 41.7-fold reduction in error with respect to the largest power of the independent variable used as an input to compute an er(cid:102)(x) function.
关键词： Programmable system on chip (PSoC),programmable logic device,genetic algorithm,power series
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 26th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Hangzhou, China (2019.7.2-2019.7.5)] 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA) - Degradation behaviour of electrical properties of inverted metamorphic four-junction (IMM4J) solar cells under 1 MeV electron irradiation
摘要： In modern RF system on chips (SoCs), the digital content consumes up to 85% of the IC chip area. The recent push to integrate multiple RF-SoC cores is met with heavy resistance by the remaining RF/analog circuitry, which creates numerous strong aggressors and weak victims leading to RF performance degradation. A key such mechanism is injection pulling through parasitic coupling between various LC-tank oscillators as well as between them and strong transmitter (TX) outputs. Any static or dynamic frequency proximity between aggressors (i.e., oscillators and TX outputs) and victims (i.e., oscillators) that share the same die causes injection pulling, which produces unwanted spurs and/or modulation distortion. In this paper, we propose and demonstrate a new frequency planning technique of a multicore TX where each LC-tank oscillator is separated from other aggressors beyond its pulling range. This is done by breaking the integer harmonic frequency relationship of victims/aggressors within and between the RF transmission channels using digital fractional divider based on a phase rotation. Each oscillator’s center frequency can be fractionally separated by ～28% but, at the same time, both producing closely spaced frequencies at the phase rotator outputs. The injection-pulling spurs are so far away that they are insigni?cantly small (?80 dBc) and coincide with the second harmonic of the carrier. This method is experimentally veri?ed in a two-channel system in 65-nm digital CMOS, each channel comprising a high-swing class-C oscillator, frequency divider, and phase rotator.
关键词： digitally controlled oscillator (DCO),Digital fractional divider,RF-SoC,multi-core radio,frequency pulling,system on chip (SoC),injection locking
更新于2025-09-19 17:13:59
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Rearrangeable and exchangeable optical module with system-on-chip for wearable functional near-infrared spectroscopy system
摘要： We developed a system-on-chip (SoC)-incorporated light-emitting diode (LED) and avalanche photo-diode (APD) modules to improve the usability and flexibility of a fiberless wearable functional near-infrared spectroscopy (fNIRS) system. The SoC has a microprocessing unit and programmable circuits. The time division method and the lock-in method were used for separately detecting signals from different positions and signals of different wavelengths, respectively. Each module autonomously works for this time-divided-lock-in measurement with a high sensitivity for haired regions. By supplying t3.3 V of power and base and data clocks, the LED module emits both 730- and 855-nm wavelengths of light, amplitudes of which are modulated in each lock-in frequency generated from the base clock, and the APD module provides the lock-in detected signals synchronizing with the data clock. The SoC provided many functions, including automatic-power-control of the LED, automatic judgment of detected power level, and automatic-gain-control of the programmable gain amplifier. The number and the arrangement of modules can be adaptively changed by connecting this exchangeable modules in a daisy chain and setting the parameters dependent on the probing position. Therefore, users can configure a variety of arrangements (single- or multidistance combinations) of them with this module-based system.
关键词： wearable,functional near-infrared spectroscopy,system-on-chip,module-based system
更新于2025-09-10 09:29:36
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[IEEE 2018 Global Internet of Things Summit (GIoTS) - Bilbao, Spain (2018.6.4-2018.6.7)] 2018 Global Internet of Things Summit (GIoTS) - Lighting IoT Test Environment (LITE) Platform: Evaluating Light-Powered, Energy HarvestingEmbedded Systems
摘要： As interest in the Internet of Things (IoT) grows, so does the requirement for distributed sensing, computation, and communication. Some projections reach a scale of over a trillion wireless devices, which creates a battery replacement challenge that is unsustainable for both human resources (replacement effort) and the environment (disposal). One ?eld of research that strives to meet this challenge is energy harvesting (EH) for self-powered systems. Photovoltaic (PV) cells enable EH capabilities and provide high energy density. They are also typically inexpensive, often making them the transducer of choice for self-powered systems. However, the performance of these EH nodes is rarely evaluated under realistic IoT environmental conditions, such as variable indoor lighting. Under low light, PV cells draw very little power and could place the self-powered system in a standby or even nonfunctional state. Most evaluations of EH systems in various lighting environments use software simulations to predict the behaviour of these nodes, but approximate models lack the exactness required to help with veri?cation of hardware in real conditions. Another approach is user testing in the ?eld, but this arduous solution would incur a variety of costs. This paper presents a third alternative: the Lighting IoT Test Environment (LITE) platform. The LITE platform is a tool that provides insight on how light-powered EH systems operate in low lighting environments. The LITE platform is able to physically emulate a variety of indoor and outdoor lighting sources with a novel mapping technique and provide time-series, environmental simulation of that source on a device under test (DUT). The light source emulation and time-series simulation capabilities are characterized with a worst case mean absolute percentage error (MAPE) of 3.2% and MAPE of 0.5%, respectively. By enabling engineers to accurately understand how these self-powered systems work under real world conditions, the LITE platform will better equip them to design, debug, and distribute fully functional and sustainable IoT nodes.
关键词： internet of things,test platform,system on chip,embedded systems,photovoltaic,energy harvesting,veri?cation
更新于2025-09-10 09:29:36