[IEEE 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - Tainan, Taiwan (2018.11.5-2018.11.7)] 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) - A Sub-Picosecond Hybrid DLL for Large-Scale Phased Array Synchronization

摘要： A large-scale timing synchronization scheme for scalable phased arrays is presented. This approach utilizes a DLL co-designed with a subsequent 2.5GHz PLL. The DLL employs a low noise, fine/coarse delay tuning to reduce the in-band rms jitter to 323fs, an order of magnitude improvement over previous works at similar frequencies. The DLL was fabricated in a 65nm bulk CMOS process and was characterized from 27MHz to 270MHz. It consumes up to 3.3mW from a 1V power supply and has a small footprint of 0.036mm2.