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) van der Waals Heterojunctions
摘要： Van der Waals heterojunctions (vdWHs) have gained extensive attention because they can integrate the excellent characteristics of the stacked materials and most vdWHs exhibit type-II band alignment. However, type-III vdWHs with broken gaps are still very rare, which limits the development and application of two-dimensional (2D) materials in the fields of tunnel FETs (TFETs). Here, we theoretically demonstrate that 2D phosphorene/SnS2 (SnSe2) vdWHs possess type-III (broken-gap) band alignment, and their I-V curves present negative differential resistance (NDR) effects. The BTBT transport mechanism and its applications in TFETs are analyzed. Interestingly, a positive electric field can enlarge the tunnelling window and a negative electric field can realize multiple-band-alignment transformation (type I, type II, and type III). Thus, this work presents the intrinsic physics mechanism and electric field tunable multiple-band alignments in 2D type-III vdWHs and related electronic devices.
关键词： tunnel FETs,SnS2,phosphorene,type-III band alignment,Van der Waals heterojunctions,electric field,SnSe2
更新于2025-09-09 09:28:46
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[IEEE 2018 IEEE Symposium on VLSI Technology - Honolulu, HI (2018.6.18-2018.6.22)] 2018 IEEE Symposium on VLSI Technology - Record 47 mV/dec top-down vertical nanowire InGaAs/GaAsSb tunnel FETs
摘要： Pocketed vertical nanowire InGaAs/GaAsSb tunnel FETs (TFET) with sub-threshold swing (SS) reaching 47 mV/dec are demonstrated. The achieved sub-threshold performance is the steepest reported so far for a top-down TFET in the III-V material system. Smooth vertical wires with diameters as narrow as 30 nm are achieved using a CH4 based dry etch process. Drive current at 0.35 V supply voltage approaches 0.7 μA/μm for a fixed Ioff of 1 nA/μm.
关键词： tunnel FETs,InGaAs/GaAsSb,vertical nanowire,sub-threshold swing,III-V material system
更新于2025-09-04 15:30:14
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX, USA (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Design Guidelines and Limitations of Multilayer Two-dimensional Vertical Tunneling FETs for UltraLow Power Logic Applications
摘要： New designs for vertical 2D-materials-based TFETs are proposed in this paper adopting asymmetric layer numbers for the top and bottom layer with undoped source/drain using Black Phosphorus as an example. The results show that abrupt turn-on and Ion/Ioff > 105 can be sustained when the channel length is down to sub-5 nm. The results are benchmarked against other TFETs based on promising 2D materials homo-/hetero-structures, meanwhile, the limitations, as well as guidelines, are presented.
关键词： DFT,tunnel FETs,Non-equilibrium Green’s Function,TMDCs,black phosphorus,Two-dimensional Materials Heterojunctions
更新于2025-09-04 15:30:14