研究目的
Investigating the fabrication of high-performance polycrystalline GeSn (poly-GeSn) junctionless thin-film transistors (JL-TFTs) at low process temperatures for next-generation electronics.
研究成果
The fabrication of high-performance poly-GeSn JL-TFTs at low process temperatures is demonstrated, with significant improvements in device performance through interface passivation. The study highlights the potential of these devices for next-generation electronics.
研究不足
The study is limited by the technical constraints of achieving high-quality poly-GeSn films on insulators at low process temperatures and the potential for optimization in device performance.
1：Experimental Design and Method Selection:
The study employs cosputtering and pulsed laser annealing (PLA) techniques to prepare poly-GeSn thin films.
2：Sample Selection and Data Sources:
Amorphous GeSn (a-GeSn) with different Sn chemical contents are deposited on Si substrates covered with 800 nm SiO2 films by magnetron cosputtering.
3：List of Experimental Equipment and Materials:
Includes a 248 nm KrF excimer laser for PLA, magnetron sputtering chamber, and atomic layer deposition (ALD) for gate stack deposition.
4：Experimental Procedures and Operational Workflow:
The process involves deposition of a-GeSn films, PLA treatment, device patterning, and characterization.
5：Data Analysis Methods:
The crystallinity and morphology of the GeSn films are characterized by Raman spectroscopy, X-ray diffraction (XRD) patterns, scanning electron microscopy (SEM), and atomic force microscopy (AFM).
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