研究目的
Demonstration of monolithically integrated light-emitting diode (LED) and quasi-vertical U-shaped trench-gate metal-oxide-semiconductor field-effect transistor (UMOSFET) in GaN, and study of the effect of FET sizing on integrated pairs.
研究成果
A prototype platform of GaN quasi-vertical power UMOSFETs and GaN LEDs monolithic optoelectronic integration has been demonstrated using selective epi removal with a 12 masking step fabrication process. The integrated pairs show controllable modulation of LED current and light output power by VDD and VGS. An integrated UMOSFET/3-LED chain is also demonstrated. The trade-off model of FET/LED power ratio η and area ratio α is given, which will be instructive to future researchers on FET/LED integration techniques.
研究不足
The relatively high off-state leakage needs improvement in future generation devices. The integrable LED turns on at 5 V, higher than the typical 3 V, which could possibly be solved by using indium tin oxide (ITO) for better current spreading in anode contact.
1：Experimental Design and Method Selection:
The study used selective epi removal (SER) approach on an LED-on-FET epi stack on sapphire substrates. Individual p-GaN layers were used for LED and FET in the design.
2：Sample Selection and Data Sources:
The starting LED-on-FET epi was grown on 2-inch sapphire substrates by metal organic chemical vapor deposition (MOCVD).
3：List of Experimental Equipment and Materials:
The fabrication process involved BCl3/Cl2 inductively coupled plasma (ICP) etch, atomic layer deposition (ALD) for gate SiO2, and low pressure chemical vapor deposition (LPCVD) for n+ polysilicon gate electrode.
4：Experimental Procedures and Operational Workflow:
The process included p-GaN activation, selective-area LED-epi etch, formation of gate, body, drain and isolation trenches, and deposition of inter-layer dielectric (ILD) SiO
5：Data Analysis Methods:
The study analyzed the output characteristics of UMOSFET/LED integrated pairs and the effect of FET sizing on integrated pairs.
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