研究目的
To achieve disruptive advances in the packaging cost, scalability in the optical port count, and scalability in the manufacturing volume for silicon photonics by leveraging existing microelectronics packaging facilities.
研究成果
The study demonstrates a novel direction in photonic packaging that leverages existing microelectronics packaging facilities, achieving high coupling efficiencies and alignment accuracies. This approach promises disruptive improvements in packaging cost, scalability, and manufacturing volume for silicon photonics.
研究不足
The placement uncertainty of high-throughput pick and place tools and the handling capability limitations for photonic components are key challenges. The approaches require mode engineering and self-alignment schemes to overcome these limitations.
1:Experimental Design and Method Selection:
The study leverages existing microelectronics packaging facilities for photonic assembly, using self-alignment to compensate for placement inaccuracies. Two approaches to fiber-to-chip interfacing and one to hybrid photonic integration are demonstrated.
2:Sample Selection and Data Sources:
The experiments involve standard cleaved fibers and photonic dies, with data collected on coupling efficiencies and alignment accuracies.
3:List of Experimental Equipment and Materials:
High-throughput pick and place tools, silicon photonic chips, standard cleaved fibers, and flip-chip assembly materials are used.
4:Experimental Procedures and Operational Workflow:
The process includes assembling fiber stubs to V-groove arrays on chips, using self-alignment for accurate placement, and measuring transmission efficiencies.
5:Data Analysis Methods:
Coupling efficiencies and alignment accuracies are analyzed to evaluate the performance of the packaging approaches.
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