研究目的
Investigating the feasibility of fabricating back-gated graphene field-effect transistors (GFETs) on 10 nm thermal SiO2 substrate and comparing the mobility of graphene devices at different locations of the transferred CVD graphene.
研究成果
The feasibility of wafer scale graphene field effect devices on thin thermal oxide substrate is demonstrated. The devices exhibit an average mobility of ~1500 cm2/V·s with minimal unintentional doping. The devices are stable with a lower operating voltage (±8 V). The dielectric thickness can be further scaled down to meet the requirements of the current technology node. The contact resistance is comparable to earlier reported values in literature.
研究不足
The minor hysteresis present could further be reduced by lowering the defect sites present in the vicinity of graphene channel. The possibility of not completely removing the PMMA residue by UHV annealing.
1：Experimental Design and Method Selection:
Back-gate GFETs were fabricated on 10 nm thermal SiO2/Si substrate using CVD graphene grown on Cu foil. The breakdown field of the 10 nm thermal SiO2 was evaluated by making MIM structures.
2：Sample Selection and Data Sources:
CVD graphene grown on Cu foil was transferred onto the SiO2/Si substrate using the conventional transfer using PMMA scaffold.
3：List of Experimental Equipment and Materials:
Raman spectroscopy with a 532 nm wavelength laser, DM01 Veeco Dimension 5000 AFM, Karl Suss MA6B contact printer, e-beam evaporation process, ALD process (Cambridge Nanotech Savannah 200).
4：0). Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: UHV annealing at 300 °C for 3 hr, conventional photolithography, metal deposition, lift-off process, ALD process at 250 °C, annealing in N2 ambient at 200 °C for 2 hours.
5：Data Analysis Methods:
Field effect mobility was extracted using the model proposed by Kim et.al by symmetrically fitting the hole and electron branches simultaneously.
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