研究目的
Investigating the growth and fabrication of top-down highly doped n + InAs(Si)/p + GaSb(Si) Esaki tunneling diodes on (001) GaAs substrates, focusing on the behavior of dislocations in highly mismatched III-Sb growth and their impact on device fabrication.
研究成果
The study demonstrates the feasibility of fabricating sub-30 nm III-V vertical NW tunneling devices on commercial GaAs substrates, despite the challenges posed by dislocations in highly mismatched growth. Two approaches for achieving low TD density GaSb layers are proposed, highlighting the potential for future III-V TFET integration on commercial substrates.
研究不足
The study is limited by the challenges in accurately determining in-plane relaxation for thin layers and the inability to reveal all dislocations with the current etching technique. The impact of dislocations on device performance is not fully quantified.
1：Experimental Design and Method Selection:
The study involves the growth of III-Sb buffer layers on GaAs substrates using MBE, with a focus on minimizing threading dislocation densities. Techniques include RHEED, AFM, XRD, and TEM for structural analysis.
2：Sample Selection and Data Sources:
Samples are grown on 2 in. (001) p+ GaAs substrates using a III–V Riber MBE 49 chamber. Growth conditions vary to study the effect on dislocation behavior.
3：List of Experimental Equipment and Materials:
Equipment includes a Bruker AFM machine, X’Pert PANalytical XRD tool, and Titan G2 aberration corrected TEM. Materials include GaAs substrates, GaSb, and InAs layers.
4：Experimental Procedures and Operational Workflow:
The process involves substrate deoxidation, GaAs layer growth, GaSb growth under varying conditions, and InAs layer deposition. Device fabrication includes a novel alcohol-based digital etch technique.
5：Data Analysis Methods:
Analysis involves comparing AFM, XRD, and TEM results to calculate threading dislocation densities and their impact on device performance.
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