1：Experimental Design and Method Selection:

The study involves the fabrication of top gated epitaxial graphene p-n junctions using exfoliated hexagonal boron nitride (h-BN) as the gate dielectric. The methodology includes the exploration of parameter spaces (B field, gate voltages, temperature) to understand the conditions for accurate resistance quantization.

2：Sample Selection and Data Sources:

Epitaxial graphene is grown on silicon carbide (SiC) chips. The samples are evaluated with confocal laser scanning and optical microscopy to identify large areas of successful growth.

3：List of Experimental Equipment and Materials:

Equipment includes a graphite-lined resistive-element furnace for the annealing process, atomic force microscope (AFM) for imaging, and a direct current comparator (DCC) resistance bridge for measurements. Materials include SiC chips, hydrofluoric acid, deionized water, and h-BN flakes.

4：Experimental Procedures and Operational Workflow:

The process involves sample growth, fabrication of Hall bar geometry and contact pads, transfer of h-BN flakes onto the graphene device, and electron beam lithography for metal deposition. Measurements of longitudinal and Hall resistances are conducted under various conditions.

5：Data Analysis Methods:

Data analysis involves converting resistance measurements into carrier densities and mobilities, and fitting models to experimental data to understand the behavior of the p-n junctions under different conditions.