研究目的
To measure the input capacitances Cgs and Cgd of SiC and GaN power FETs to improve simulation models for better mapping of drain-source voltage vds and drain current id during switching operation.
研究成果
The paper presents a generalized extraction process for the inter-electrode input capacitance Cgd(vgd) and Cgs(vgs) of WBG power FETs, independent of boundary conditions. The method is validated through measurements on SiC and GaN devices, showing good agreement with small signal datasheet values. The approach significantly improves the matching of current and voltage waveforms during switching operations for various operating points.
研究不足
The approach is sensitive to parasitic capacitances and inductances, requiring a low inductive, low parasitic capacitance test bench for accurate measurements. The method's accuracy is also influenced by the gate current measurement precision, especially in the sub-nanocoulomb area.
1：Experimental Design and Method Selection:
The methodology involves measuring the gate charge characteristic at an inductive load condition with varying drain current values and temperature settings to allocate gate current to Cgd and Cgs charging.
2：Sample Selection and Data Sources:
Commercially available SiC and GaN devices with a drain current rating of approximately 15 A are used.
3：List of Experimental Equipment and Materials:
Includes a test bench setup with specific parameters for gate charge measurements, considering parasitic capacitances and inductances.
4：Experimental Procedures and Operational Workflow:
The process involves capturing the gate charge characteristic during turn-on operation under inductive load, determining Cgs and Cgd characteristics.
5：Data Analysis Methods:
The gate current is analyzed to separate the charging currents of Cgd and Cgs, with post-processing to account for parasitic capacitances.
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