研究目的
To demonstrate and compare TG-SA a-IGZO TFTs with different light shielding metal designs, analyze their electrical characteristics and reliability, and evaluate their application in OLED displays.
研究成果
TG-SA a-IGZO TFTs with SM designs, especially those connected to the gate electrode (TB TFTs), show improved electrical performance and stability under bias stresses. The prototype OLED display demonstrated excellent quality, indicating good mass-production potential. Future work could optimize SM designs further and explore scalability.
研究不足
The study is limited to specific SM designs and sizes; variations in other parameters or environmental conditions were not fully explored. The small sample size for SH=18 in reliability tests may affect credibility, and the fabrication process is specific to G2.5 production line, which may not generalize to other scales.
1：Experimental Design and Method Selection:
The study involved fabricating TG-SA a-IGZO TFTs with various SM designs (connected to source or gate electrode, different sizes) and without SMs to analyze their effects on electrical characteristics and reliability under PBTS and NBIS tests. Theoretical models include charge trapping mechanisms and double-gate structure effects.
2：Sample Selection and Data Sources:
Samples were fabricated on 370 mm × 470 mm glass substrates, with a-IGZO layer (In:Ga:Zn=1:1:1 at%) and other layers deposited via sputtering and PECVD. Electrical measurements were conducted using an Agilent semiconductor analyzer system.
3：List of Experimental Equipment and Materials:
Equipment includes DC sputter for shield layer deposition, PECVD for SiOx and SiO2 layers, sputtering for electrodes, and Agilent semiconductor analyzer for measurements. Materials include glass substrates, a-IGZO, SiOx, SiO2, Cu for electrodes, and organic layers for passivation.
4：Experimental Procedures and Operational Workflow:
Fabrication steps: deposit shield layer by DC sputter, deposit SiOx buffer layer by PECVD, deposit a-IGZO layer by DC sputtering, deposit SiO2 gate insulator by PECVD, deposit and pattern ILD, form gate and S/D electrodes by sputtering, and complete with passivation and other layers. Measurements of transfer characteristics and stress tests (PBTS and NBIS) were performed.
5：Data Analysis Methods:
Electrical parameters such as threshold voltage (VTH), sub-threshold swing (SS), saturation current (Ion), and VTH shifts under stress were analyzed. Statistical comparison of different SM designs was conducted based on measured data.
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