研究目的
To develop and implement a skeletonization algorithm for 2-D gray scale images on FPGA for computer vision applications, focusing on improving performance in real-time image processing.
研究成果
The proposed algorithm and FPGA architecture successfully skeletonize 2-D gray scale images with low latency and high performance, achieving a maximum frequency of 207.684 MHz on a Xilinx Vertex 5 board. This method is applicable to pattern recognition and computer vision, with potential for extension to 3-D images.
研究不足
The implementation was tested only for an 8x8 image size; scalability to larger images depends on FPGA memory capacity. The algorithm may not be suitable for all image shapes and requires optimization for real-time VLSI implementations due to computational complexity.
1：Experimental Design and Method Selection:
The study designed a novel algorithm for skeletonizing 2-D gray scale images using a 3x3 windowing operator and implemented it on an FPGA. The architecture includes dual port memory, main controller, read and write count controllers, RAMs, and processing elements for parallel processing.
2：Sample Selection and Data Sources:
An 8x8 image size was used for testing, with pixel values read from an external source and stored in memory. The approach can be scaled to any image size (MxN) if FPGA memory is sufficient.
3：List of Experimental Equipment and Materials:
Xilinx Vertex 5 FPGA board, dual port RAM, FIFO registers, counters, and processing elements were used.
4：Experimental Procedures and Operational Workflow:
The process involves reading image data, storing it in memory, accessing 3x3 windows using FIFO and counters, processing each window to identify corner and border pixels, eroding boundaries iteratively, and outputting the skeletonized image.
5：Data Analysis Methods:
Timing waveforms and device utilization summaries were analyzed to evaluate performance metrics such as execution time, frequency, and resource usage on the FPGA.
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