研究目的
To reduce leakage current in low temperature polycrystalline silicon thin film transistors (LTPS TFTs) without sacrificing field-effect mobility by using an optimized hydrogenated amorphous silicon (a-Si:H) passivation layer.
研究成果
The optimized a-Si:H passivation layer (at GR=0.75) significantly improved the electrical performance of LTPS TFTs, increasing field-effect mobility by 78.4% and reducing leakage current by passivating defect sites at poly-Si grain boundaries, without the mobility degradation seen in previous methods. This approach is promising for high-performance display applications.
研究不足
The study is limited to p-channel LTPS TFTs and specific deposition conditions; optimization of passivation layers may require further tuning for different materials or device structures. The use of hydrogen dilution could potentially create new dangling bonds if not carefully controlled.
1：Experimental Design and Method Selection:
The study involved depositing a-Si:H passivation layers on poly-Si layers using plasma enhanced chemical vapor deposition (PECVD) with varying hydrogen dilution gas ratios (GR = H2/(SiH4 + H2)) to optimize passivation quality. Structural and electrical characteristics were analyzed using Raman spectroscopy, Fourier transform infrared spectroscopy (FT-IR), and quasi-steady-state photoconductance (QSSPC) measurements. LTPS TFTs were fabricated and their electrical performance evaluated.
2：Sample Selection and Data Sources:
Samples included a-Si:H and μc-Si:H passivation layers deposited on glass substrates and single crystalline silicon wafers for characterization, and LTPS TFTs fabricated on glass substrates with different passivation layers.
3：List of Experimental Equipment and Materials:
Equipment included PECVD system for deposition, Raman spectrometer, FT-IR spectrometer, QSSPC measurement system, semiconductor parameter analyzer, and technology computer-aided design (TCAD) software for simulation. Materials included silane (SiH4), hydrogen (H2), buffer oxide, poly-Si, aluminium for gate metal, and boron for doping.
4：Experimental Procedures and Operational Workflow:
A 50-nm-thick a-Si:H film was deposited on a buffer oxide layer, dehydrogenated, crystallized with an excimer laser, and then passivation layers (10 nm thick) were deposited with varying GR. Gate insulator (SiO2) and gate metal (Al) were deposited, patterned, and doped. Electrical characteristics were measured at room temperature under dark conditions.
5：Data Analysis Methods:
Data were analyzed using Raman peak ratios, FT-IR absorption peaks, carrier lifetime from QSSPC, and electrical parameters (mobility, subthreshold swing, leakage current) extracted from transfer curves. TCAD simulation was used to model defect states.
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