1：Experimental Design and Method Selection:

The study involved fabricating CMUTs using SOI wafers and conducting static and dynamic capacitance measurements under DC and AC excitation to analyze dielectric charging effects. Theoretical models and 3D FEA were used for comparison.

2：Sample Selection and Data Sources:

A batch of CMUTs was fabricated as a 6x6 planar array with specific geometric parameters (e.g., diaphragm sidelength of 225 μm, thickness of 2 μm, airgap of 1 μm). Data were collected from experimental measurements using an LCR meter and SEM inspections.

3：List of Experimental Equipment and Materials:

Equipment included an Agilent E4980A LCR meter for capacitance measurements, SEM for geometric characterization, electron-beam evaporator for metal deposition, DRIE system for silicon etching, and critical point dryer. Materials included SOI wafers, chromium, gold, Shipley 1805 photoresist, HMDS primer, and various etching solutions (e.g., Transene TFA, Transene 1020, Improved BOE).

4：Experimental Procedures and Operational Workflow:

Fabrication involved RCA cleaning, metal deposition, photolithography, etching of layers, DRIE for silicon, sacrificial oxide etching, and critical point drying. Measurements included static capacitance at zero bias and with varying DC bias, pitch-catch mode testing with bias and AC excitation, and SEM for thickness and warping assessment.

5：Data Analysis Methods:

Data were analyzed by comparing experimental capacitance values with analytical calculations, using curve fitting and statistical deviation analysis. Leakage currents and heating effects were qualitatively assessed.