研究目的
To determine the physical mechanism responsible for the weak inversion capacitance-voltage (C-V) hump phenomenon in n-InGaAs based metal-oxide-semiconductor (MOS) gate stacks.
研究成果
The weak inversion C-V hump in n-InGaAs based MOS gate stacks is determined to be a capacitance footprint of carrier interaction between interface states and the semiconductor conduction band, not the inversion layer. This is due to a near exponential increase of donorlike interface states density toward the valence band. The C-V hump can serve as a qualitative indicator of interface quality for gate stacks with similar dielectric capacitance.
研究不足
The study is limited to n-InGaAs based MOS structures and may not generalize to other semiconductors. The C-V hump interpretation depends on dielectric capacitance, requiring similar capacitance for reliable interface quality assessment. The simulation assumes specific interface state distributions and response times, which may vary in real devices.
1：Experimental Design and Method Selection:
The study involved fabricating MOS capacitors on n-InGaAs, performing capacitance-voltage (C-V) and conductance-voltage (G-V) measurements, and simulating the mechanisms using equivalent circuits to compare with experimental results. Theoretical models included equivalent circuits for ideal MOS structures and those with interface states interacting with one or both semiconductor bands.
2：Sample Selection and Data Sources:
Samples used were n-type Sn-doped (6×10^16 cm^-3) In0.53Ga0.47As layers (500 nm) grown by metal-organic molecular beam epitaxy on n-type heavily doped (~10^18 cm^-3) InP (100) substrates.
3：53Ga47As layers (500 nm) grown by metal-organic molecular beam epitaxy on n-type heavily doped (~10^18 cm^-3) InP (100) substrates.
List of Experimental Equipment and Materials:
3. List of Experimental Equipment and Materials: Equipment included a Picosun SUNALE? system for dielectric deposition, ellipsometry for thickness measurement, electron beam evaporation for electrode deposition, and an Agilent E4980A impedance analyzer for C-V and G-V measurements. Materials included acetone, methanol, propanol, de-ionized water, diluted H2SO4, NH4OH, trimethylaluminum (TMA), NH3 plasma, water, Cr, Au, Al2O3, and AlN.
4：Experimental Procedures and Operational Workflow:
Sample cleaning involved sequential treatments in acetone, methanol, propanol, DI water, diluted H2SO4, DI water, and NH4OH. After drying, samples were transferred to the deposition chamber, treated with TMA pulses, and dielectric films (Al2O3 or Al2O3/AlN) were deposited. Electrodes were deposited by electron beam evaporation, followed by postmetallization annealing. C-V and G-V measurements were conducted in the dark at room temperature over 400 Hz–1 MHz with a small signal voltage amplitude of 0.025 V, corrected for series resistance.
5：025 V, corrected for series resistance.
Data Analysis Methods:
5. Data Analysis Methods: Data analysis involved simulating capacitance and conductance using equivalent circuits, comparing with experimental results, and interpreting the mechanisms based on interface state interactions and response times.
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