- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images
摘要： Space missions are facing disruptive innovation since the appearance of small, lightweight, and low-cost satellites (e.g., CubeSats). The use of commercial devices and their limitations in cost usually entail a decrease in available on-board computing power. To face this change, the on-board processing paradigm is advancing towards the clustering of satellites, and moving to distributed and collaborative schemes in order to maintain acceptable performance levels in complex applications such as hyperspectral image processing. In this scenario, hybrid hardware/software and reconfigurable computing have appeared as key enabling technologies, even though they increase complexity in both design and run time. In this paper, the ARTICo3 framework, which abstracts and eases the design and run-time management of hardware-accelerated systems, has been used to deploy a networked implementation of the Fast UNmixing (FUN) algorithm, which performs linear unmixing of hyperspectral images in a small cluster of reconfigurable computing devices that emulates a distributed on-board processing scenario. Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways: on the one hand, in the number of accelerators per reconfigurable device; on the other hand, in the number of network nodes. Experimental results motivate the use of ARTICo3-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation. Results also show that the proposed implementation may be better, for certain configurations, than an equivalent software-based solution in both performance and energy efficiency, achieving great scalability that is only limited by communication bandwidth.
关键词： FPGAs,hyperspectral imaging,on-board processing,ARTICo3,linear unmixing
更新于2025-09-23 15:23:52
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FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors
摘要： In recent years, using distributed fiber-optic sensors based on Brillouin scattering, for monitoring pipelines, tunnels, and other constructional structures have gained huge popularity. However, these sensors have a low signal-to-noise ratio (SNR), which usually increases their measurement error. To alleviate this issue, ensemble averaging is used which improves the SNR but in return increases the measurement time. Reducing the noise by averaging requires hundreds or thousands of scans of the optical fiber; hence averaging is usually responsible for a large percent of the entire system latency. In this paper, we propose a novel method based on artificial neural network for SNR enhancement and measurement acceleration in distributed fiber-optic sensors based on the Brillouin scattering. Our method takes the noisy Brillouin spectrums and improves their SNR by 20 dB, which reduces the measurement time significantly. It also improves the accuracy of the Brillouin frequency shift estimation process and its latency by more than 50% in comparison with the state-of-the-art software and hardware solutions.
关键词： Artificial neural network (ANN),digital signal processing,optical fibers,curve fitting,field-programmable gate arrays (FPGAs)
更新于2025-09-23 15:23:52
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Scalable Hardware-Based On-Board Processing for Run-Time Adaptive Lossless Hyperspectral Compression
摘要： Hyperspectral data processing is a computationally intensive task that is usually performed in high-performance computing clusters. However, in remote sensing scenarios, where communications are expensive, a compression stage is required at the edge of data acquisition before transmitting information to ground stations for further processing. Moreover, hyperspectral image compressors need to meet minimum performance and energy-efficiency levels to cope with the real-time requirements imposed by the sensors and the available power budget. Hence, they are usually implemented as dedicated hardware accelerators in expensive space-grade electronic devices. In recent years though, these devices have started to coexist with low-cost commercial alternatives in which unconventional techniques, such as run-time hardware reconfiguration are evaluated within research-oriented space missions (e.g., CubeSats). In this paper, a run-time reconfigurable implementation of a low-complexity lossless hyperspectral compressor (i.e., CCSDS 123) on a commercial off-the-shelf device is presented. The proposed approach leverages an FPGA-based on-board processing architecture with a data-parallel execution model to transparently manage a configurable number of resource-efficient hardware cores, dynamically adapting both throughput and energy efficiency. The experimental results show that this solution is competitive when compared with the current state-of-the-art hyperspectral compressors and that the impact of the parallelization scheme on the compression rate is acceptable when considering the improvements in terms of performance and energy consumption. Moreover, scalability tests prove that run-time adaptation of the compression throughput and energy efficiency can be achieved by modifying the number of hardware accelerators, a feature that can be useful in space scenarios, where requirements change over time (e.g., communication bandwidth or power budget).
关键词： dynamic and partial reconfiguration,FPGAs,Data compression,high-performance embedded computing,on-board processing,hyperspectral images
更新于2025-09-19 17:15:36
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Bi-Junction Carrier Depletion Type Electro-Optic Phase-Shifters
摘要： Silicon photonic integrated circuits (PICs) combine dense optical system integration with industrial scalability by adopting well-established CMOS fabrication processes. An electro-optic phaseshifter (EOP) represents a basic building unit of several PICs applications, including datacom optical switches, PIC-FPGAs, and beam steering. In-situ resistive-heaters in close vicinity of waveguides, or free-carrier injection/depletion in doped junctions, are common methods to build EOPs. Literature reports thermal shifters consuming 24.7 mW to achieve DC large signal π-phaseshift, power consumption of injection PIN implementations and depletion PN modulators of 10 mW and ≈ 0 mW respectively. A thermal EOP naturally avoids carrier-induced optical insertion losses (IL), in contrast to a PIN/PN modulator. Thus, thermal and PIN/PN methods trade-off IL with electrical power rather than minimizing both. An EOP of low optical losses and low electrical power is highly desired in large-signal, and low-speed applications.
关键词： electro-optic phaseshifter,datacom optical switches,PIC-FPGAs,beam steering,CMOS fabrication,Silicon photonic integrated circuits
更新于2025-09-11 14:15:04