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Gate Bias and Length Dependences of Total-Ionizing-Dose Effects in InGaAs FinFETs on Bulk Si
摘要： We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS FinFETs with different gate lengths irradiated with 10-keV X-rays under different gate biases. The largest degradation after irradiation occurs at VG = -1 V. Radiation-induced trapped positive charge dominates the TID response of InGaAs FinFET transistors, consistent with previous results for InGaAs multi-fin capacitors. Shorter gate-length devices show larger radiation-induced charge trapping than longer gate-length devices, most likely due to the electrostatic effects of trapped charge in the surrounding SiO2 isolation and SiO2/Si3N4 spacer oxides. 1/f noise measurements indicate a high trap density and a non-uniform defect-energy distribution, consistent with a strong variation of effective border-trap density with surface potential.
关键词： 1/f noise,FinFETs,InGaAs,Total-Ionizing-Dose,Bulk Si,border-trap,Gate length dependence,III-V
更新于2025-09-19 17:15:36
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[IEEE 48th European Solid-State Device Research Conference (ESSDERC 2018) - Dresden (2018.9.3-2018.9.6)] 2018 48th European Solid-State Device Research Conference (ESSDERC) - InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance
摘要： In this paper, we demonstrate InGaAs FinFETs 3D sequentially (3DS) integrated on top of a fully-depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. The low thermal budget of the top layer process caused no performance degradation of the lower level FETs. Record ION of 200 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V) for 3DS integrated III-V FETs on silicon is demonstrated, with a 50% reduction of RON compared to previous work. The achieved improved performance can be attributed to the introduction of doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.
关键词： 3DS,monolithic integration,wafer bonding,III-V,sequential integration,FinFETs
更新于2025-09-04 15:30:14