- 标题
- 摘要
- 关键词
- 实验方案
- 产品
-
Vertical GaN Schottky barrier diodes on Ge-doped free-standing GaN substrates
摘要： Vertical GaN Schottky barrier diodes (SBDs) were fabricated on Ge-doped free-standing GaN substrates grown by hydride vapor phase epitaxy. Detailed material characterization was performed, and the results indicate the superiority of Ge doping in the GaN, which contributed to the SBDs with lower stress, fewer defects and higher quality. Based on the capacitance-voltage and currentevoltage measurements performed, SBDs achieved together with a low turn-on voltage Von (0.71e0.74 V), high current Ion/Ioff ratio (3.9 (cid:1) 107e2.9 (cid:1) 108), high Schottky barrier height (0.96e0.99 eV), and high breakdown voltage Vb (802 V for a 100 mm diameter). This shows that vertical GaN SBDs on the Ge-doped substrates are promising candidates for high power applications.
关键词： GaN device,Vertical SBDs,Low turn-on voltage,Ge-doped GaN substrates,High breakdown voltage
更新于2025-09-23 15:23:52
-
High Breakdown Strength Schottky Diodes Made from Electrodeposited ZnO for Power Electronics Applications
摘要： The synthesis of ZnO films by optimized electrodeposition led to the achievement of a critical electric field of 800 kV/cm. This value, which is 2 to 3 times higher than in monocrystalline silicon, was derived from a vertical Schottky diode application of columnar-structured ZnO films electrodeposited on platinum. The device exhibited a free carrier concentration of 2.5 × 10^15 cm^-3, a rectification ratio of 3 × 10^8 and an ideality factor of 1.10, a value uncommonly obtained in solution-processed ZnO. High breakdown strength and high thickness capability make this environment-friendly process a serious option for power electronics and energy-harvesting.
关键词： breakdown voltage,electrodeposition,zinc oxide,critical electric field,solution-processed,Schottky diode,power diode,ideality factor
更新于2025-09-23 15:23:52
-
[IEEE 2018 IEEE Third Ecuador Technical Chapters Meeting (ETCM) - Cuenca, Ecuador (2018.10.15-2018.10.19)] 2018 IEEE Third Ecuador Technical Chapters Meeting (ETCM) - Reliability in GaN-based devices for power applications
摘要： This paper analyzes two important reliability issues in AlGaN/GaN devices: positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB). The summarized results of our previous PBTI studies in MOS-HEMTs show that the threshold voltage degradation in devices with SiO2 as gate dielectric is characterized by a universal decreasing behavior of the trapping rate parameter and is ascribed to charge trapping in the SiO2 and at the SiO2/GaN interface. On the contrary, the degradation observed in Al2O3- and AlN/Al2O3-gate stacks is mainly attributed to charge capture in the pre-existing dielectric traps with a negligible interface state generation. Additionally, the insertion of a thin AlN layer impacts on the device reliability because larger trap density, faster charge trapping, wider trap energy distribution and slower charge release are observed compared with devices without this layer. The dielectric importance of GaN-based devices has been also investigated in Schottky Barrier Diodes (SBDs) with a gated edge termination (GET). Our recent TDDB results indicate a narrower Weibull distribution, and a longer time to failure in devices with a double GET layer structure and with a thick passivation layer (2 GET-THICK) than in single GET devices with a thin passivation (1 GET-THIN). Therefore, the former structure is more suitable for high-power and high-temperature applications.
关键词： TDDB,AlGaN/GaN SBD,trapping,de-trapping,reliability,PBTI,breakdown voltage,GET,MOS-HEMT
更新于2025-09-23 15:23:52
-
Influence of GaN- and Si?N?-Passivation Layers on the Performance of AlGaN/GaN Diodes With a Gated Edge Termination
摘要： This paper analyses the influence of the GaN and Si3N4 passivation (or 'cap') layer on the top of the AlGaN barrier layer on the performance and reliability of Schottky barrier diodes with a gated edge termination (GET-SBDs). Both GaN cap and Si3N4 cap devices show similar dc characteristics but a higher density of traps at the SiO2/GaN interface or/and an increase of the total dielectric constant in the access region result in higher RON-dispersion in GaN cap devices. The leakage current at medium/low temperatures in both types of devices shows two low-voltage-independent activation energies, suggesting thermionic and field-emission processes to be responsible for the conduction. Furthermore, a voltage-dependent activation energy in the high-temperature range occurs from low voltages in the GaN cap devices and limits their breakdown voltage (VBD). Time-dependent dielectric breakdown measurements show a tighter distribution in Si3N4 cap devices (Weibull slope β = 3.3) compared to GaN cap devices (β = 1.8). Additional measurements in plasma-enhanced atomic layer deposition (PEALD)-Si3N4 capacitors with different cap layers and TCAD simulations show an electric field distribution with a strong peak within the PEALD-Si3N4 dielectric at the GET corner, which could accelerate the formation of a percolation path and provoke the device breakdown in GaN cap SBDs even at low-stress voltages.
关键词： Si3N4 cap,GaN cap,AlGaN/GaN Schottky diode,reliability,breakdown voltage,passivation layer,off-state,Activation energy
更新于2025-09-23 15:23:52
-
Performance analysis of a novel trench SOI LDMOS with centrosymmetric double vertical field plates
摘要： A novel trench SOI LDMOS with centrosymmetric double vertical field plates structure (CDVFPT SOI LDMOS) is proposed in this paper. The 2-D device simulator MEDICI is used to investigate the characteristics of the proposed structure. Compared with the conventional trench SOI LDMOS (CT SOI LDMOS), the optimized device shows an obvious reduction in the specific on-resistance (Ron,sp) when its breakdown voltage (BV) is enhanced due to the introduction of centrosymmetric double vertical field plates structure. And when compared to previous device with floating vertical field plate trench SOI LDMOS (FVFPT SOI LDMOS), the overall performance of CDVFPT SOI LDMOS is also promoted. According to the simulation results, compared to a CT SOI LDMOS, the BV of CDVFPT SOI LDMOS increases from 188 V to 234 V. The Ron,sp, however, decreases from 2.30 mΩ·cm2 to 1.24 mΩ·cm2. In addition, the maximum lattice temperature at 1 mW/μm2 is slightly reduced.
关键词： Power MOSFET,Specific on-resistance,Vertical field plate,Breakdown voltage
更新于2025-09-23 15:23:52
-
Impact of strained silicon on the device performance of a bipolar charge plasma transistor
摘要： In this manuscript we analyze a unique approach to improve the performance of the bipolar charge plasma transistor (BCPT) by introducing a strained Si/SixGe1?x layer as the active device region. For charge plasma realization different metal work-function electrodes are used to induce n+ and p+ regions on undoped strained silicon-on-insulator (sSOI or SixGe1?x) to realize emitter, base, and collector regions of the BCPT. Here, by using a calibrated 2-D TCAD simulation the impact of a Si mole fraction x (in SixGe1?x) on device performance metrics is investigated. The analysis demonstrates the band gap lowering with decreasing Si content or effective strain on the Si layer, and its subsequent advantages. This work reports a significant improvement in current gain, cutoff frequency, and lower collector breakdown voltage (BVCEO) for the proposed structure over the conventional device. The effect of varying temperature on the strained Si layer and its implications on the device performance is also investigated. The analysis demonstrates a fair device-level understanding and exhibits the immense potential of the SixGe1?x material as the device layer. In addition to this, using extensive 2-D mixed-mode TCAD simulation, a considerable improvement in switching transient times are also observed compared to its conventional counterpart.
关键词： bipolar charge plasma transistor (BCPT),mole fraction,cutoff frequency (fT),current gain (β),collector breakdown voltage (BVCEO),strained Si layer,band gap lowering
更新于2025-09-23 15:23:52
-
[IEEE 2017 9th IEEE-GCC Conference and Exhibition (GCCCE) - Manama, Bahrain (2017.5.8-2017.5.11)] 2017 9th IEEE-GCC Conference and Exhibition (GCCCE) - Polarization Engineered Enhancement Mode High Breakdown Voltage GaN CAVET
摘要： In this work we propose and simulate a polarization engineered enhancement mode current aperture vertical electron transistor (P-CAVET). The novelty of the proposed structure lies in using polarization engineering to achieve enhancement mode operation. The current blocking layer (CBL) of proposed P-CAVET is hybrid in nature and consist of an oxide part and AlN part. Aluminum Nitride (AlN) portion of CBL is used to lift the triangular well existing at AlGaN/GaN interface above the Fermi level, thus achieving the enhancement mode operation. The CBL provides better suppression of vertical leakage which improves the breakdown voltage. The proposed structure does not need any p-type doping either for achieving enhancement mode operation or for forming current blocking layer. A 2-D calibrated simulation study has revealed that the proposed device exhibits a threshold voltage of 3.1V and breakdown voltage improvement of 100% over the conventional device CAVET.
关键词： Polarization Engineering,Breakdown Voltage,CAVET,CBL,GaN
更新于2025-09-23 15:22:29
-
Different Isolation Processes for Free-Standing GaN p-n Power Diode with Ultra-High Current Injection
摘要： In this article, we report on the fabrication and high performance of power p-n diodes grown on free-standing (FS) GaN substrate. The key technique to enhance the high breakdown voltage and suppress the surface leakage current is the isolation process. The mesa-structure diode is generally formed by utilizing the inductively coupled plasma reactive ion etching (ICP-RIE); however, it always induces high surface damages and thus causes a high leakage current. In this study, we propose a planar structure by employing the oxygen ion implantation to frame the isolation region. By following the crucial process, the fabricated mesa- and planar-type diodes exhibit the turn-on voltages of 3.5 and 3.7 V, specific on-resistance (RONA) of 0.42 and 0.46 mΩ-cm2, and breakdown voltage (VB) of 2640 and 2880 V, respectively. The corresponding Baliga’s figures of merit (BFOM, i.e., VB2/RONA) are 16.6 and 18 GW/cm2, respectively. The BFOM of 18 GW/cm2 is the highest reported value for FS-GaN diode. From the temperature dependent measurements, the planar-type diode also shows the better leakage current and thermal stability than the mesa-type diode.
关键词： leakage current,Baliga’s figure of merit,breakdown voltage,planar diode,implantation,GaN substrate
更新于2025-09-23 15:22:29
-
Step-Double-Zone-JTE for SiC Devices with Increased Tolerance to JTE Dose and Surface Charges
摘要： In this paper, an edge termination structure, referred to as step-double-zone junction termination extension (Step-DZ-JTE), is proposed. Step-DZ-JTE further improves the distribution of the electric field (EF) by its own step shape. Step-DZ-JTE and other termination structures are investigated for comparison using numerical simulations. Step-DZ-JTE greatly reduces the sensitivity of breakdown voltage (BV) and surface charges (SC). For a 30-μm thick epi-layer, the optimized Step-DZ-JTE shows 90% of the theoretical BV with a wide tolerance of 12.2 × 10^12 cm^?2 to the JTE dose and 85% of the theoretical BV with an improved tolerance of 3.7 × 10^12 cm^?2 to the positive SC are obtained. Furthermore, when combined with the field plate technique, the performance of the Step-DZ-JTE is further improved.
关键词： breakdown voltage (BV),edge termination,junction termination extension (JTE),silicon carbide (SiC)
更新于2025-09-23 15:22:29
-
[IEEE 2018 31st International Vacuum Nanoelectronics Conference (IVNC) - Kyoto, Japan (2018.7.9-2018.7.13)] 2018 31st International Vacuum Nanoelectronics Conference (IVNC) - Arrays of Si Field Emitter Individually Regulated by Si Nanowires High Breakdown Voltages and Enhanced Performance
摘要： We fabricate Si field emitter arrays (FEAs) with integrated Si nanowire current limiters and investigate a method to enable higher voltage operation, which can potentially increase achievable current densities. In this work, we focus on the dielectric breakdown occurring in the vicinity of the nanopillar. A deeper etch is shown to increase the breakdown voltage but at the expense of poorer field emission characteristics possibly due to the loss of mechanical support or increased surface states.
关键词： field emitter arrays,Silicon,breakdown voltage,current limiters
更新于2025-09-23 15:21:21