研究目的
Investigating the synthesis method of energy-efficient FSMs implemented in PLD circuits using local clock gating to reduce dynamic power consumption.
研究成果
The method based on clock gating is the most efficient one, leading to significant reduction of dynamic power consumed by the FSM. The conclusions can be applied to any synchronous circuit, not just those implemented in PLDs.
研究不足
The research was dedicated to logic circuits using PLDs as the implementation platform. The effectiveness of the proposed methods was verified by simulation experiments, which may not cover all real-world scenarios.
1：Experimental Design and Method Selection:
The study compares three methods of implementing sequential circuits in PLDs with respect to clock distribution: classical fully synchronous structure, structure exploiting Enable Clock inputs, and structure using clock gating.
2：Sample Selection and Data Sources:
The experiments were conducted on simple synchronous circuits: binary counter, classical ring counter, and Johnson counter.
3：List of Experimental Equipment and Materials:
PLDs from Altera (CPLD device 5M2210ZF324I5 and FPGA EP4CE22E22C7), Quartus II Plus v. 13.1 software, Riviera-Pro 2016.02 simulator, PowerPlay Power Analyzer.
4：1 software, Riviera-Pro 02 simulator, PowerPlay Power Analyzer.
Experimental Procedures and Operational Workflow:
4. Experimental Procedures and Operational Workflow: Circuits were synthesized, simulated, and power was analyzed using the mentioned tools.
5：Data Analysis Methods:
Comparison of Core Dynamic Power for all analyzed circuits was presented in bar charts.
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