1：Experimental Design and Method Selection:

The study involves fabricating back-gated MoS2 FETs with SiO2 gate dielectrics of different thicknesses and HfO2 encapsulation layers to investigate the influence of trapped charges on device performance. Theoretical models related to charged impurity scattering and screening effects are employed.

2：Sample Selection and Data Sources:

Heavily doped p++ silicon wafers are used as substrates, with SiO2 films of 10 nm, 20 nm, 30 nm, and 40 nm thicknesses grown by dry oxidation. MoS2 flakes are obtained from bulk crystal via micromechanical cleavage and transferred onto substrates. About 16 transistors per group are fabricated for statistical analysis.

3：List of Experimental Equipment and Materials:

Equipment includes atomic force microscopy (AFM) for surface roughness evaluation, spectroscopic ellipsometry for thickness measurement, electron beam lithography (EBL) for patterning, thermal evaporation for electrode deposition, rapid thermal annealing system, and Keithley 4200-SCS semiconductor parameter analyzer for electrical measurements. Materials include SiO2, HfO2, MoS2 bulk crystal, Cr/Au for electrodes, and Scotch tape for transfer.

4：Experimental Procedures and Operational Workflow:

Clean silicon wafers, grow SiO2 films, transfer MoS2 flakes, pattern source and drain regions using EBL, deposit Cr/Au electrodes, perform rapid thermal annealing in N2 ambient, and measure current-voltage characteristics in a light-tight, shielded condition.

5：Data Analysis Methods:

Extract parameters such as ON/OFF ratio, threshold voltage, and field-effect mobility from transfer curves using linear extrapolation and equation μFE = (L / (Cox W Vds)) * (dIds / dVgs). Statistical averaging is applied to mitigate variations.