1：Experimental Design and Method Selection:

The study aims to induce unipolar n-type conduction in BP transistors by depositing a 20-nm-thick MgO layer using atomic layer deposition (ALD). The rationale is to modify the Schottky barrier and enable electron injection while suppressing hole conduction. Theoretical models include thermionic emission for barrier height extraction.

2：Sample Selection and Data Sources:

Few-layer BP flakes with thicknesses ranging from 2.6 to 7.6 nm were prepared by mechanical exfoliation onto a p++ Si substrate with a 50-nm ALD Al2O3 dielectric. Electrical characterizations were performed at room temperature and low temperatures.

3：6 to 6 nm were prepared by mechanical exfoliation onto a p++ Si substrate with a 50-nm ALD Al2O3 dielectric. Electrical characterizations were performed at room temperature and low temperatures. List of Experimental Equipment and Materials:

3. List of Experimental Equipment and Materials: Equipment includes an ALD system for MgO and Al2O3 deposition, electron beam lithography (EBL) for patterning, electron beam evaporation for metal deposition (Ti/Au contacts), a Cascade probe station with an HP4155B analyzer for room temperature measurements, and a Lakeshore probe station with a Keithley 4200 SCS analyzer for low-temperature measurements. Materials include BP flakes, Al2O3 dielectric, MgO capping layer, Ti (5 nm)/Au (70 nm) metal contacts, and precursors for ALD (Bis(Ethylcyclopentadienyl)Magnesium and H2O for MgO).

4：Experimental Procedures and Operational Workflow:

BP flakes were exfoliated onto the Al2O3/Si substrate. Source/drain electrodes were patterned using EBL and deposited via electron beam evaporation. For the experimental group, a 20-nm MgO layer was deposited by ALD at 150°C, followed by a 20-nm Al2O3 capping layer for all devices to prevent degradation. Electrical measurements were conducted under ambient conditions or in vacuum for low temperatures, with transfer and output characteristics recorded over time.

5：Data Analysis Methods:

Data analysis involved calculating extrinsic electron mobility using the equation μ = L/(W Vds Cg) * dIds/dVgs in the linear regime, extracting threshold voltages by linear extrapolation, and determining Schottky barrier heights from Arrhenius plots of ln(Ids/T^{3/2}) versus 1000/T at various gate biases.